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14c735c8e3
On Amlogic GX SoCs, there is two CEC controllers : - An Amlogic CEC custom in the AO domain - The Synopsys HDMI-TX Controller in the EE domain Each of these controllers needs a 32.768KHz clock, but there is two paths : - In the EE domain, the "32k_clk" this patchs is adding - In the AO domain, with a more complex dual divider more precise setup The AO 32K clock support will be pushed later in the corresponding gxbb-aoclk driver when the AE CEC driver is ready. The EE 32k_clk must be pushed earlier since mainline support for CEC in the Synopsys HDMI-TX controller is nearby. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [Rebased patch on top of last changes] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
297 lines
12 KiB
C
297 lines
12 KiB
C
/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (c) 2016 AmLogic, Inc.
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* Author: Michael Turquette <mturquette@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING
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*
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* BSD LICENSE
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*
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* Copyright (c) 2016 BayLibre, Inc.
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* Author: Michael Turquette <mturquette@baylibre.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __GXBB_H
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#define __GXBB_H
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/*
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* Clock controller register offsets
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*
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* Register offsets from the data sheet are listed in comment blocks below.
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* Those offsets must be multiplied by 4 before adding them to the base address
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* to get the right value
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*/
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#define SCR 0x2C /* 0x0b offset in data sheet */
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#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
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#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
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#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
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#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
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#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
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#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
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#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */
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#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
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#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
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#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */
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#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */
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#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */
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#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
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#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
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#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
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#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
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#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
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#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
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#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
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#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */
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#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
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#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */
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#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
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#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
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#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */
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#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
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#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */
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#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
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#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
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#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */
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#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */
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#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
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#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */
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#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */
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#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */
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#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */
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#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */
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#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */
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#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */
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#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */
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#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */
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#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */
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#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */
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#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
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#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
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#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */
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#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */
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#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */
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#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
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#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
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#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
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#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
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#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
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#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
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#define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset in data sheet */
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#define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset in data sheet */
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#define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset in data sheet */
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#define HHI_MPLL_CNTL10 0x2A4 /* MP2, 0xa9 offset in data sheet */
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#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */
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#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */
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#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
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#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
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#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
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#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */
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#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */
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#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */
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#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */
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#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */
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#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */
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#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
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#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
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#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
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#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
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#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
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#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
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#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */
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#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */
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#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */
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#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */
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#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */
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#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */
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#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */
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#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */
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#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */
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/*
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* CLKID index values
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*
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* These indices are entirely contrived and do not map onto the hardware.
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* Migrate them out of this header and into the DT header file when they need
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* to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
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*/
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#define CLKID_SYS_PLL 0
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/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
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/* CLKID_HDMI_PLL */
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#define CLKID_FIXED_PLL 3
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/* CLKID_FCLK_DIV2 */
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/* CLKID_FCLK_DIV3 */
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/* CLKID_FCLK_DIV4 */
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#define CLKID_FCLK_DIV5 7
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#define CLKID_FCLK_DIV7 8
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/* CLKID_GP0_PLL */
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#define CLKID_MPEG_SEL 10
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#define CLKID_MPEG_DIV 11
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/* CLKID_CLK81 */
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#define CLKID_MPLL0 13
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#define CLKID_MPLL1 14
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/* CLKID_MPLL2 */
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#define CLKID_DDR 16
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#define CLKID_DOS 17
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#define CLKID_ISA 18
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#define CLKID_PL301 19
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#define CLKID_PERIPHS 20
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/* CLKID_SPICC */
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/* CLKID_I2C */
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/* #define CLKID_SAR_ADC */
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#define CLKID_SMART_CARD 24
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/* CLKID_RNG0 */
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/* CLKID_UART0 */
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#define CLKID_SDHC 27
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#define CLKID_STREAM 28
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#define CLKID_ASYNC_FIFO 29
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#define CLKID_SDIO 30
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#define CLKID_ABUF 31
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#define CLKID_HIU_IFACE 32
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#define CLKID_ASSIST_MISC 33
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/* CLKID_SPI */
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#define CLKID_I2S_SPDIF 35
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/* CLKID_ETH */
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#define CLKID_DEMUX 37
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/* CLKID_AIU_GLUE */
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/* CLKID_IEC958 */
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/* CLKID_I2S_OUT */
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#define CLKID_AMCLK 41
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#define CLKID_AIFIFO2 42
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#define CLKID_MIXER 43
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/* CLKID_MIXER_IFACE */
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#define CLKID_ADC 45
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#define CLKID_BLKMV 46
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/* CLKID_AIU */
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/* CLKID_UART1 */
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#define CLKID_G2D 49
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/* CLKID_USB0 */
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/* CLKID_USB1 */
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#define CLKID_RESET 52
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#define CLKID_NAND 53
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#define CLKID_DOS_PARSER 54
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/* CLKID_USB */
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#define CLKID_VDIN1 56
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#define CLKID_AHB_ARB0 57
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#define CLKID_EFUSE 58
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#define CLKID_BOOT_ROM 59
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#define CLKID_AHB_DATA_BUS 60
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#define CLKID_AHB_CTRL_BUS 61
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#define CLKID_HDMI_INTR_SYNC 62
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/* CLKID_HDMI_PCLK */
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/* CLKID_USB1_DDR_BRIDGE */
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/* CLKID_USB0_DDR_BRIDGE */
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#define CLKID_MMC_PCLK 66
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#define CLKID_DVIN 67
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/* CLKID_UART2 */
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/* #define CLKID_SANA */
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#define CLKID_VPU_INTR 70
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#define CLKID_SEC_AHB_AHB3_BRIDGE 71
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#define CLKID_CLK81_A53 72
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#define CLKID_VCLK2_VENCI0 73
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#define CLKID_VCLK2_VENCI1 74
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#define CLKID_VCLK2_VENCP0 75
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#define CLKID_VCLK2_VENCP1 76
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/* CLKID_GCLK_VENCI_INT0 */
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#define CLKID_GCLK_VENCI_INT 78
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#define CLKID_DAC_CLK 79
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/* CLKID_AOCLK_GATE */
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/* CLKID_IEC958_GATE */
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#define CLKID_ENC480P 82
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#define CLKID_RNG1 83
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#define CLKID_GCLK_VENCI_INT1 84
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#define CLKID_VCLK2_VENCLMCC 85
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#define CLKID_VCLK2_VENCL 86
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#define CLKID_VCLK_OTHER 87
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#define CLKID_EDP 88
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#define CLKID_AO_MEDIA_CPU 89
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#define CLKID_AO_AHB_SRAM 90
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#define CLKID_AO_AHB_BUS 91
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#define CLKID_AO_IFACE 92
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/* CLKID_AO_I2C */
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/* CLKID_SD_EMMC_A */
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/* CLKID_SD_EMMC_B */
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/* CLKID_SD_EMMC_C */
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/* CLKID_SAR_ADC_CLK */
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/* CLKID_SAR_ADC_SEL */
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#define CLKID_SAR_ADC_DIV 99
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/* CLKID_MALI_0_SEL */
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#define CLKID_MALI_0_DIV 101
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/* CLKID_MALI_0 */
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/* CLKID_MALI_1_SEL */
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#define CLKID_MALI_1_DIV 104
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/* CLKID_MALI_1 */
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/* CLKID_MALI */
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/* CLKID_CTS_AMCLK */
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#define CLKID_CTS_AMCLK_SEL 108
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#define CLKID_CTS_AMCLK_DIV 109
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/* CLKID_CTS_MCLK_I958 */
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#define CLKID_CTS_MCLK_I958_SEL 111
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#define CLKID_CTS_MCLK_I958_DIV 112
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/* CLKID_CTS_I958 */
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#define CLKID_32K_CLK 114
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#define CLKID_32K_CLK_SEL 115
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#define CLKID_32K_CLK_DIV 116
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#define NR_CLKS 117
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/* include the CLKIDs that have been made part of the stable DT binding */
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#include <dt-bindings/clock/gxbb-clkc.h>
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#endif /* __GXBB_H */
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