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With our current support for the new MIO PCI instructions, write combining/write back MMIO memory can be obtained via the pci_iomap_wc() and pci_iomap_wc_range() functions. This is achieved by using the write back address for a specific bar as provided in clp_store_query_pci_fn() These functions are however not widely used and instead drivers often rely on ioremap_wc() and ioremap_prot(), which on other platforms enable write combining using a PTE flag set through the pgrprot value. While we do not have a write combining flag in the low order flag bits of the PTE like x86_64 does, with MIO support, there is a write back bit in the physical address (bit 1 on z15) and thus also the PTE. Which bit is used to toggle write back and whether it is available at all, is however not fixed in the architecture. Instead we get this information from the CLP Store Logical Processor Characteristics for PCI command. When the write back bit is not provided we fall back to the existing behavior. Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.ibm.com> Reviewed-by: Gerald Schaefer <gerald.schaefer@linux.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
83 lines
2.2 KiB
C
83 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* S390 version
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* Copyright IBM Corp. 1999
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* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
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*
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* Derived from "include/asm-i386/io.h"
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*/
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#ifndef _S390_IO_H
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#define _S390_IO_H
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#include <linux/kernel.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/pci_io.h>
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#define xlate_dev_mem_ptr xlate_dev_mem_ptr
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void *xlate_dev_mem_ptr(phys_addr_t phys);
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#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
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void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#define IO_SPACE_LIMIT 0
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void __iomem *ioremap_prot(phys_addr_t addr, size_t size, unsigned long prot);
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void __iomem *ioremap(phys_addr_t addr, size_t size);
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void __iomem *ioremap_wc(phys_addr_t addr, size_t size);
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void __iomem *ioremap_wt(phys_addr_t addr, size_t size);
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void iounmap(volatile void __iomem *addr);
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static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
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{
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return NULL;
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}
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static inline void ioport_unmap(void __iomem *p)
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{
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}
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#ifdef CONFIG_PCI
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/*
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* s390 needs a private implementation of pci_iomap since ioremap with its
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* offset parameter isn't sufficient. That's because BAR spaces are not
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* disjunctive on s390 so we need the bar parameter of pci_iomap to find
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* the corresponding device and create the mapping cookie.
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*/
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#define pci_iomap pci_iomap
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#define pci_iomap_range pci_iomap_range
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#define pci_iounmap pci_iounmap
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#define pci_iomap_wc pci_iomap_wc
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#define pci_iomap_wc_range pci_iomap_wc_range
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#define ioremap ioremap
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#define ioremap_wt ioremap_wt
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#define ioremap_wc ioremap_wc
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#define memcpy_fromio(dst, src, count) zpci_memcpy_fromio(dst, src, count)
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#define memcpy_toio(dst, src, count) zpci_memcpy_toio(dst, src, count)
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#define memset_io(dst, val, count) zpci_memset_io(dst, val, count)
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#define mmiowb() zpci_barrier()
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#define __raw_readb zpci_read_u8
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#define __raw_readw zpci_read_u16
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#define __raw_readl zpci_read_u32
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#define __raw_readq zpci_read_u64
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#define __raw_writeb zpci_write_u8
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#define __raw_writew zpci_write_u16
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#define __raw_writel zpci_write_u32
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#define __raw_writeq zpci_write_u64
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#endif /* CONFIG_PCI */
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#include <asm-generic/io.h>
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#endif
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