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44babea2ea
Run the automatic pad calibration after voltage switching if tegra_host->pad_calib_required is set. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
941 lines
28 KiB
C
941 lines
28 KiB
C
/*
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* Copyright (C) 2010 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/iopoll.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/gpio/consumer.h>
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#include "sdhci-pltfm.h"
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/* Tegra SDHOST controller vendor register definitions */
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#define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100
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#define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000
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#define SDHCI_CLOCK_CTRL_TAP_SHIFT 16
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#define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5)
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#define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3)
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#define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2)
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#define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
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#define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
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#define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
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#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
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#define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
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#define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4
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#define SDHCI_AUTO_CAL_START BIT(31)
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#define SDHCI_AUTO_CAL_ENABLE BIT(29)
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#define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff
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#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0
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#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f
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#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7
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#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31)
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#define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec
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#define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31)
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#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
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#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
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#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
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#define NVQUIRK_ENABLE_SDR50 BIT(3)
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#define NVQUIRK_ENABLE_SDR104 BIT(4)
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#define NVQUIRK_ENABLE_DDR50 BIT(5)
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#define NVQUIRK_HAS_PADCALIB BIT(6)
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#define NVQUIRK_NEEDS_PAD_CONTROL BIT(7)
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struct sdhci_tegra_soc_data {
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const struct sdhci_pltfm_data *pdata;
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u32 nvquirks;
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};
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/* Magic pull up and pull down pad calibration offsets */
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struct sdhci_tegra_autocal_offsets {
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u32 pull_up_3v3;
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u32 pull_down_3v3;
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u32 pull_up_3v3_timeout;
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u32 pull_down_3v3_timeout;
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u32 pull_up_1v8;
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u32 pull_down_1v8;
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u32 pull_up_1v8_timeout;
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u32 pull_down_1v8_timeout;
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u32 pull_up_sdr104;
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u32 pull_down_sdr104;
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u32 pull_up_hs400;
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u32 pull_down_hs400;
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};
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struct sdhci_tegra {
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const struct sdhci_tegra_soc_data *soc_data;
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struct gpio_desc *power_gpio;
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bool ddr_signaling;
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bool pad_calib_required;
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bool pad_control_available;
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struct reset_control *rst;
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struct pinctrl *pinctrl_sdmmc;
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struct pinctrl_state *pinctrl_state_3v3;
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struct pinctrl_state *pinctrl_state_1v8;
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struct sdhci_tegra_autocal_offsets autocal_offsets;
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};
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static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
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if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
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(reg == SDHCI_HOST_VERSION))) {
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/* Erratum: Version register is invalid in HW. */
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return SDHCI_SPEC_200;
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}
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return readw(host->ioaddr + reg);
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}
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static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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switch (reg) {
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case SDHCI_TRANSFER_MODE:
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/*
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* Postpone this write, we must do it together with a
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* command write that is down below.
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*/
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pltfm_host->xfer_mode_shadow = val;
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return;
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case SDHCI_COMMAND:
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writel((val << 16) | pltfm_host->xfer_mode_shadow,
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host->ioaddr + SDHCI_TRANSFER_MODE);
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return;
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}
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writew(val, host->ioaddr + reg);
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}
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static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
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/* Seems like we're getting spurious timeout and crc errors, so
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* disable signalling of them. In case of real errors software
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* timers should take care of eventually detecting them.
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*/
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if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
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val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
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writel(val, host->ioaddr + reg);
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if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
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(reg == SDHCI_INT_ENABLE))) {
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/* Erratum: Must enable block gap interrupt detection */
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u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
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if (val & SDHCI_INT_CARD_INT)
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gap_ctrl |= 0x8;
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else
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gap_ctrl &= ~0x8;
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writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
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}
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}
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static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
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{
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return mmc_gpio_get_ro(host->mmc);
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}
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static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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int has_1v8, has_3v3;
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/*
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* The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad
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* voltage configuration in order to perform voltage switching. This
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* means that valid pinctrl info is required on SDHCI instances capable
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* of performing voltage switching. Whether or not an SDHCI instance is
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* capable of voltage switching is determined based on the regulator.
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*/
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if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))
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return true;
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if (IS_ERR(host->mmc->supply.vqmmc))
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return false;
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has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
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1700000, 1950000);
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has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
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2700000, 3600000);
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if (has_1v8 == 1 && has_3v3 == 1)
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return tegra_host->pad_control_available;
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/* Fixed voltage, no pad control required. */
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return true;
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}
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static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
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u32 misc_ctrl, clk_ctrl, pad_ctrl;
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sdhci_reset(host, mask);
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if (!(mask & SDHCI_RESET_ALL))
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return;
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misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
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clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
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misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 |
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SDHCI_MISC_CTRL_ENABLE_SDR50 |
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SDHCI_MISC_CTRL_ENABLE_DDR50 |
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SDHCI_MISC_CTRL_ENABLE_SDR104);
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clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
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if (tegra_sdhci_is_pad_and_regulator_valid(host)) {
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/* Erratum: Enable SDHCI spec v3.00 support */
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if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
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misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
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/* Advertise UHS modes as supported by host */
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if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
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misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
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if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
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misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
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if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
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misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
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if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50)
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clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
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}
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sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
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sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
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if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) {
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pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
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pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK;
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pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL;
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sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
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tegra_host->pad_calib_required = true;
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}
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tegra_host->ddr_signaling = false;
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}
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static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable)
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{
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u32 val;
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/*
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* Enable or disable the additional I/O pad used by the drive strength
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* calibration process.
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*/
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val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
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if (enable)
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val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
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else
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val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
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sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
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if (enable)
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usleep_range(1, 2);
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}
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static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable)
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{
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bool status;
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u32 reg;
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reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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status = !!(reg & SDHCI_CLOCK_CARD_EN);
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if (status == enable)
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return status;
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if (enable)
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reg |= SDHCI_CLOCK_CARD_EN;
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else
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reg &= ~SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
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return status;
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}
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static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host,
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u16 pdpu)
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{
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u32 reg;
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reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
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reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK;
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reg |= pdpu;
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sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
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}
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static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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struct sdhci_tegra_autocal_offsets offsets =
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tegra_host->autocal_offsets;
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struct mmc_ios *ios = &host->mmc->ios;
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bool card_clk_enabled;
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u16 pdpu;
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u32 reg;
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int ret;
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switch (ios->timing) {
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case MMC_TIMING_UHS_SDR104:
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pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104;
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break;
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case MMC_TIMING_MMC_HS400:
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pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400;
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break;
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default:
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if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
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pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8;
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else
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pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3;
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}
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tegra_sdhci_set_pad_autocal_offset(host, pdpu);
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card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
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tegra_sdhci_configure_cal_pad(host, true);
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reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
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reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
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sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
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usleep_range(1, 2);
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/* 10 ms timeout */
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ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS,
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reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE),
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1000, 10000);
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tegra_sdhci_configure_cal_pad(host, false);
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tegra_sdhci_configure_card_clk(host, card_clk_enabled);
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if (ret) {
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dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n");
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if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
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pdpu = offsets.pull_down_1v8_timeout << 8 |
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offsets.pull_up_1v8_timeout;
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else
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pdpu = offsets.pull_down_3v3_timeout << 8 |
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offsets.pull_up_3v3_timeout;
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/* Disable automatic calibration and use fixed offsets */
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reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
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reg &= ~SDHCI_AUTO_CAL_ENABLE;
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sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
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tegra_sdhci_set_pad_autocal_offset(host, pdpu);
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}
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}
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static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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struct sdhci_tegra_autocal_offsets *autocal =
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&tegra_host->autocal_offsets;
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int err;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-up-offset-3v3",
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&autocal->pull_up_3v3);
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if (err)
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autocal->pull_up_3v3 = 0;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-down-offset-3v3",
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&autocal->pull_down_3v3);
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if (err)
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autocal->pull_down_3v3 = 0;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-up-offset-1v8",
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&autocal->pull_up_1v8);
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if (err)
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autocal->pull_up_1v8 = 0;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-down-offset-1v8",
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&autocal->pull_down_1v8);
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if (err)
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autocal->pull_down_1v8 = 0;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-up-offset-3v3-timeout",
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&autocal->pull_up_3v3);
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if (err)
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autocal->pull_up_3v3_timeout = 0;
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err = device_property_read_u32(host->mmc->parent,
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"nvidia,pad-autocal-pull-down-offset-3v3-timeout",
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&autocal->pull_down_3v3);
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if (err)
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autocal->pull_down_3v3_timeout = 0;
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|
|
err = device_property_read_u32(host->mmc->parent,
|
|
"nvidia,pad-autocal-pull-up-offset-1v8-timeout",
|
|
&autocal->pull_up_1v8);
|
|
if (err)
|
|
autocal->pull_up_1v8_timeout = 0;
|
|
|
|
err = device_property_read_u32(host->mmc->parent,
|
|
"nvidia,pad-autocal-pull-down-offset-1v8-timeout",
|
|
&autocal->pull_down_1v8);
|
|
if (err)
|
|
autocal->pull_down_1v8_timeout = 0;
|
|
|
|
err = device_property_read_u32(host->mmc->parent,
|
|
"nvidia,pad-autocal-pull-up-offset-sdr104",
|
|
&autocal->pull_up_sdr104);
|
|
if (err)
|
|
autocal->pull_up_sdr104 = autocal->pull_up_1v8;
|
|
|
|
err = device_property_read_u32(host->mmc->parent,
|
|
"nvidia,pad-autocal-pull-down-offset-sdr104",
|
|
&autocal->pull_down_sdr104);
|
|
if (err)
|
|
autocal->pull_down_sdr104 = autocal->pull_down_1v8;
|
|
|
|
err = device_property_read_u32(host->mmc->parent,
|
|
"nvidia,pad-autocal-pull-up-offset-hs400",
|
|
&autocal->pull_up_hs400);
|
|
if (err)
|
|
autocal->pull_up_hs400 = autocal->pull_up_1v8;
|
|
|
|
err = device_property_read_u32(host->mmc->parent,
|
|
"nvidia,pad-autocal-pull-down-offset-hs400",
|
|
&autocal->pull_down_hs400);
|
|
if (err)
|
|
autocal->pull_down_hs400 = autocal->pull_down_1v8;
|
|
}
|
|
|
|
static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
|
|
{
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
|
|
unsigned long host_clk;
|
|
|
|
if (!clock)
|
|
return sdhci_set_clock(host, clock);
|
|
|
|
/*
|
|
* In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI
|
|
* divider to be configured to divided the host clock by two. The SDHCI
|
|
* clock divider is calculated as part of sdhci_set_clock() by
|
|
* sdhci_calc_clk(). The divider is calculated from host->max_clk and
|
|
* the requested clock rate.
|
|
*
|
|
* By setting the host->max_clk to clock * 2 the divider calculation
|
|
* will always result in the correct value for DDR50/52 modes,
|
|
* regardless of clock rate rounding, which may happen if the value
|
|
* from clk_get_rate() is used.
|
|
*/
|
|
host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
|
|
clk_set_rate(pltfm_host->clk, host_clk);
|
|
if (tegra_host->ddr_signaling)
|
|
host->max_clk = host_clk;
|
|
else
|
|
host->max_clk = clk_get_rate(pltfm_host->clk);
|
|
|
|
sdhci_set_clock(host, clock);
|
|
|
|
if (tegra_host->pad_calib_required) {
|
|
tegra_sdhci_pad_autocalib(host);
|
|
tegra_host->pad_calib_required = false;
|
|
}
|
|
}
|
|
|
|
static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
|
|
unsigned timing)
|
|
{
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
|
|
|
|
if (timing == MMC_TIMING_UHS_DDR50 ||
|
|
timing == MMC_TIMING_MMC_DDR52)
|
|
tegra_host->ddr_signaling = true;
|
|
|
|
sdhci_set_uhs_signaling(host, timing);
|
|
}
|
|
|
|
static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
|
|
{
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
|
|
return clk_round_rate(pltfm_host->clk, UINT_MAX);
|
|
}
|
|
|
|
static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
|
|
reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
|
|
reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
|
|
sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
|
|
}
|
|
|
|
static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
|
|
{
|
|
unsigned int min, max;
|
|
|
|
/*
|
|
* Start search for minimum tap value at 10, as smaller values are
|
|
* may wrongly be reported as working but fail at higher speeds,
|
|
* according to the TRM.
|
|
*/
|
|
min = 10;
|
|
while (min < 255) {
|
|
tegra_sdhci_set_tap(host, min);
|
|
if (!mmc_send_tuning(host->mmc, opcode, NULL))
|
|
break;
|
|
min++;
|
|
}
|
|
|
|
/* Find the maximum tap value that still passes. */
|
|
max = min + 1;
|
|
while (max < 255) {
|
|
tegra_sdhci_set_tap(host, max);
|
|
if (mmc_send_tuning(host->mmc, opcode, NULL)) {
|
|
max--;
|
|
break;
|
|
}
|
|
max++;
|
|
}
|
|
|
|
/* The TRM states the ideal tap value is at 75% in the passing range. */
|
|
tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
|
|
|
|
return mmc_send_tuning(host->mmc, opcode, NULL);
|
|
}
|
|
|
|
static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage)
|
|
{
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
|
|
int ret;
|
|
|
|
if (!tegra_host->pad_control_available)
|
|
return 0;
|
|
|
|
if (voltage == MMC_SIGNAL_VOLTAGE_180) {
|
|
ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
|
|
tegra_host->pinctrl_state_1v8);
|
|
if (ret < 0)
|
|
dev_err(mmc_dev(host->mmc),
|
|
"setting 1.8V failed, ret: %d\n", ret);
|
|
} else {
|
|
ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
|
|
tegra_host->pinctrl_state_3v3);
|
|
if (ret < 0)
|
|
dev_err(mmc_dev(host->mmc),
|
|
"setting 3.3V failed, ret: %d\n", ret);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
|
|
struct mmc_ios *ios)
|
|
{
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
|
|
int ret = 0;
|
|
|
|
if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
|
|
ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = sdhci_start_signal_voltage_switch(mmc, ios);
|
|
} else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
|
|
ret = sdhci_start_signal_voltage_switch(mmc, ios);
|
|
if (ret < 0)
|
|
return ret;
|
|
ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage);
|
|
}
|
|
|
|
if (tegra_host->pad_calib_required)
|
|
tegra_sdhci_pad_autocalib(host);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int tegra_sdhci_init_pinctrl_info(struct device *dev,
|
|
struct sdhci_tegra *tegra_host)
|
|
{
|
|
tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev);
|
|
if (IS_ERR(tegra_host->pinctrl_sdmmc)) {
|
|
dev_dbg(dev, "No pinctrl info, err: %ld\n",
|
|
PTR_ERR(tegra_host->pinctrl_sdmmc));
|
|
return -1;
|
|
}
|
|
|
|
tegra_host->pinctrl_state_3v3 =
|
|
pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3");
|
|
if (IS_ERR(tegra_host->pinctrl_state_3v3)) {
|
|
dev_warn(dev, "Missing 3.3V pad state, err: %ld\n",
|
|
PTR_ERR(tegra_host->pinctrl_state_3v3));
|
|
return -1;
|
|
}
|
|
|
|
tegra_host->pinctrl_state_1v8 =
|
|
pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8");
|
|
if (IS_ERR(tegra_host->pinctrl_state_1v8)) {
|
|
dev_warn(dev, "Missing 1.8V pad state, err: %ld\n",
|
|
PTR_ERR(tegra_host->pinctrl_state_3v3));
|
|
return -1;
|
|
}
|
|
|
|
tegra_host->pad_control_available = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
|
|
{
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
|
|
const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
|
|
|
|
if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
|
|
tegra_host->pad_calib_required = true;
|
|
}
|
|
|
|
static const struct sdhci_ops tegra_sdhci_ops = {
|
|
.get_ro = tegra_sdhci_get_ro,
|
|
.read_w = tegra_sdhci_readw,
|
|
.write_l = tegra_sdhci_writel,
|
|
.set_clock = tegra_sdhci_set_clock,
|
|
.set_bus_width = sdhci_set_bus_width,
|
|
.reset = tegra_sdhci_reset,
|
|
.platform_execute_tuning = tegra_sdhci_execute_tuning,
|
|
.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
|
|
.voltage_switch = tegra_sdhci_voltage_switch,
|
|
.get_max_clock = tegra_sdhci_get_max_clock,
|
|
};
|
|
|
|
static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
|
|
.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
|
|
SDHCI_QUIRK_SINGLE_POWER_WRITE |
|
|
SDHCI_QUIRK_NO_HISPD_BIT |
|
|
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
|
|
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
|
|
.ops = &tegra_sdhci_ops,
|
|
};
|
|
|
|
static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
|
|
.pdata = &sdhci_tegra20_pdata,
|
|
.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
|
|
NVQUIRK_ENABLE_BLOCK_GAP_DET,
|
|
};
|
|
|
|
static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
|
|
.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
|
|
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
|
|
SDHCI_QUIRK_SINGLE_POWER_WRITE |
|
|
SDHCI_QUIRK_NO_HISPD_BIT |
|
|
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
|
|
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
|
|
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
|
|
SDHCI_QUIRK2_BROKEN_HS200 |
|
|
/*
|
|
* Auto-CMD23 leads to "Got command interrupt 0x00010000 even
|
|
* though no command operation was in progress."
|
|
*
|
|
* The exact reason is unknown, as the same hardware seems
|
|
* to support Auto CMD23 on a downstream 3.1 kernel.
|
|
*/
|
|
SDHCI_QUIRK2_ACMD23_BROKEN,
|
|
.ops = &tegra_sdhci_ops,
|
|
};
|
|
|
|
static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
|
|
.pdata = &sdhci_tegra30_pdata,
|
|
.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
|
|
NVQUIRK_ENABLE_SDR50 |
|
|
NVQUIRK_ENABLE_SDR104 |
|
|
NVQUIRK_HAS_PADCALIB,
|
|
};
|
|
|
|
static const struct sdhci_ops tegra114_sdhci_ops = {
|
|
.get_ro = tegra_sdhci_get_ro,
|
|
.read_w = tegra_sdhci_readw,
|
|
.write_w = tegra_sdhci_writew,
|
|
.write_l = tegra_sdhci_writel,
|
|
.set_clock = tegra_sdhci_set_clock,
|
|
.set_bus_width = sdhci_set_bus_width,
|
|
.reset = tegra_sdhci_reset,
|
|
.platform_execute_tuning = tegra_sdhci_execute_tuning,
|
|
.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
|
|
.voltage_switch = tegra_sdhci_voltage_switch,
|
|
.get_max_clock = tegra_sdhci_get_max_clock,
|
|
};
|
|
|
|
static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
|
|
.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
|
|
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
|
|
SDHCI_QUIRK_SINGLE_POWER_WRITE |
|
|
SDHCI_QUIRK_NO_HISPD_BIT |
|
|
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
|
|
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
|
|
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
|
|
.ops = &tegra114_sdhci_ops,
|
|
};
|
|
|
|
static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
|
|
.pdata = &sdhci_tegra114_pdata,
|
|
};
|
|
|
|
static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
|
|
.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
|
|
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
|
|
SDHCI_QUIRK_SINGLE_POWER_WRITE |
|
|
SDHCI_QUIRK_NO_HISPD_BIT |
|
|
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
|
|
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
|
|
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
|
|
/*
|
|
* The TRM states that the SD/MMC controller found on
|
|
* Tegra124 can address 34 bits (the maximum supported by
|
|
* the Tegra memory controller), but tests show that DMA
|
|
* to or from above 4 GiB doesn't work. This is possibly
|
|
* caused by missing programming, though it's not obvious
|
|
* what sequence is required. Mark 64-bit DMA broken for
|
|
* now to fix this for existing users (e.g. Nyan boards).
|
|
*/
|
|
SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
|
|
.ops = &tegra114_sdhci_ops,
|
|
};
|
|
|
|
static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
|
|
.pdata = &sdhci_tegra124_pdata,
|
|
};
|
|
|
|
static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
|
|
.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
|
|
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
|
|
SDHCI_QUIRK_SINGLE_POWER_WRITE |
|
|
SDHCI_QUIRK_NO_HISPD_BIT |
|
|
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
|
|
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
|
|
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
|
|
.ops = &tegra114_sdhci_ops,
|
|
};
|
|
|
|
static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
|
|
.pdata = &sdhci_tegra210_pdata,
|
|
.nvquirks = NVQUIRK_NEEDS_PAD_CONTROL,
|
|
};
|
|
|
|
static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
|
|
.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
|
|
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
|
|
SDHCI_QUIRK_SINGLE_POWER_WRITE |
|
|
SDHCI_QUIRK_NO_HISPD_BIT |
|
|
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
|
|
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
|
|
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
|
|
/* SDHCI controllers on Tegra186 support 40-bit addressing.
|
|
* IOVA addresses are 48-bit wide on Tegra186.
|
|
* With 64-bit dma mask used for SDHCI, accesses can
|
|
* be broken. Disable 64-bit dma, which would fall back
|
|
* to 32-bit dma mask. Ideally 40-bit dma mask would work,
|
|
* But it is not supported as of now.
|
|
*/
|
|
SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
|
|
.ops = &tegra114_sdhci_ops,
|
|
};
|
|
|
|
static const struct sdhci_tegra_soc_data soc_data_tegra186 = {
|
|
.pdata = &sdhci_tegra186_pdata,
|
|
.nvquirks = NVQUIRK_NEEDS_PAD_CONTROL,
|
|
};
|
|
|
|
static const struct of_device_id sdhci_tegra_dt_match[] = {
|
|
{ .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
|
|
{ .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
|
|
{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
|
|
{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
|
|
{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
|
|
{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
|
|
|
|
static int sdhci_tegra_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *match;
|
|
const struct sdhci_tegra_soc_data *soc_data;
|
|
struct sdhci_host *host;
|
|
struct sdhci_pltfm_host *pltfm_host;
|
|
struct sdhci_tegra *tegra_host;
|
|
struct clk *clk;
|
|
int rc;
|
|
|
|
match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
|
|
if (!match)
|
|
return -EINVAL;
|
|
soc_data = match->data;
|
|
|
|
host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
|
|
if (IS_ERR(host))
|
|
return PTR_ERR(host);
|
|
pltfm_host = sdhci_priv(host);
|
|
|
|
tegra_host = sdhci_pltfm_priv(pltfm_host);
|
|
tegra_host->ddr_signaling = false;
|
|
tegra_host->pad_calib_required = false;
|
|
tegra_host->pad_control_available = false;
|
|
tegra_host->soc_data = soc_data;
|
|
|
|
if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) {
|
|
rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host);
|
|
if (rc == 0)
|
|
host->mmc_host_ops.start_signal_voltage_switch =
|
|
sdhci_tegra_start_signal_voltage_switch;
|
|
}
|
|
|
|
rc = mmc_of_parse(host->mmc);
|
|
if (rc)
|
|
goto err_parse_dt;
|
|
|
|
if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
|
|
host->mmc->caps |= MMC_CAP_1_8V_DDR;
|
|
|
|
tegra_sdhci_parse_pad_autocal_dt(host);
|
|
|
|
tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
|
|
GPIOD_OUT_HIGH);
|
|
if (IS_ERR(tegra_host->power_gpio)) {
|
|
rc = PTR_ERR(tegra_host->power_gpio);
|
|
goto err_power_req;
|
|
}
|
|
|
|
clk = devm_clk_get(mmc_dev(host->mmc), NULL);
|
|
if (IS_ERR(clk)) {
|
|
dev_err(mmc_dev(host->mmc), "clk err\n");
|
|
rc = PTR_ERR(clk);
|
|
goto err_clk_get;
|
|
}
|
|
clk_prepare_enable(clk);
|
|
pltfm_host->clk = clk;
|
|
|
|
tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
|
|
"sdhci");
|
|
if (IS_ERR(tegra_host->rst)) {
|
|
rc = PTR_ERR(tegra_host->rst);
|
|
dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
|
|
goto err_rst_get;
|
|
}
|
|
|
|
rc = reset_control_assert(tegra_host->rst);
|
|
if (rc)
|
|
goto err_rst_get;
|
|
|
|
usleep_range(2000, 4000);
|
|
|
|
rc = reset_control_deassert(tegra_host->rst);
|
|
if (rc)
|
|
goto err_rst_get;
|
|
|
|
usleep_range(2000, 4000);
|
|
|
|
rc = sdhci_add_host(host);
|
|
if (rc)
|
|
goto err_add_host;
|
|
|
|
return 0;
|
|
|
|
err_add_host:
|
|
reset_control_assert(tegra_host->rst);
|
|
err_rst_get:
|
|
clk_disable_unprepare(pltfm_host->clk);
|
|
err_clk_get:
|
|
err_power_req:
|
|
err_parse_dt:
|
|
sdhci_pltfm_free(pdev);
|
|
return rc;
|
|
}
|
|
|
|
static int sdhci_tegra_remove(struct platform_device *pdev)
|
|
{
|
|
struct sdhci_host *host = platform_get_drvdata(pdev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
|
|
|
|
sdhci_remove_host(host, 0);
|
|
|
|
reset_control_assert(tegra_host->rst);
|
|
usleep_range(2000, 4000);
|
|
clk_disable_unprepare(pltfm_host->clk);
|
|
|
|
sdhci_pltfm_free(pdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sdhci_tegra_driver = {
|
|
.driver = {
|
|
.name = "sdhci-tegra",
|
|
.of_match_table = sdhci_tegra_dt_match,
|
|
.pm = &sdhci_pltfm_pmops,
|
|
},
|
|
.probe = sdhci_tegra_probe,
|
|
.remove = sdhci_tegra_remove,
|
|
};
|
|
|
|
module_platform_driver(sdhci_tegra_driver);
|
|
|
|
MODULE_DESCRIPTION("SDHCI driver for Tegra");
|
|
MODULE_AUTHOR("Google, Inc.");
|
|
MODULE_LICENSE("GPL v2");
|