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447b0c7b93
This adds support for the mostly register-compatible SPICTRL cores from the GRLIB VHDL IP core library from Aeroflex Gaisler. They are normally running on SPARC. A different entry in of_fsl_spi_match matches this core and indicates a different hardware type that is used to set up different function pointers and special cases. The GRLIB core operates in cpu mode. The number of bits per word might be limited. There might be native chipselects selected via a slave select register. These differences to the FSL type cores, if present, are indicated by a capabilities register. Other register and function differences exists but are not relevant to the driver. Acked-by: Anton Vorontsov <anton@enomsg.org> Signed-off-by: Andreas Larsson <andreas@gaisler.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca> |
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| .. | ||
| brcm,bcm2835-spi.txt | ||
| fsl-imx-cspi.txt | ||
| fsl-spi.txt | ||
| mxs-spi.txt | ||
| nvidia,tegra20-sflash.txt | ||
| nvidia,tegra20-slink.txt | ||
| nvidia,tegra20-spi.txt | ||
| omap-spi.txt | ||
| sh-msiof.txt | ||
| spi_altera.txt | ||
| spi_atmel.txt | ||
| spi_oc_tiny.txt | ||
| spi_pl022.txt | ||
| spi-bus.txt | ||
| spi-gpio.txt | ||
| spi-octeon.txt | ||
| spi-orion.txt | ||
| spi-samsung.txt | ||
| spi-sc18is602.txt | ||