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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
289 lines
7.4 KiB
C
289 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) 2010 John Crispin <john@phrozen.org>
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* Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
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* Based on EP93xx wdt driver
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*/
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#include <linux/module.h>
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#include <linux/bitops.h>
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#include <linux/watchdog.h>
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#include <linux/of_platform.h>
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#include <linux/uaccess.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <lantiq_soc.h>
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#define LTQ_XRX_RCU_RST_STAT 0x0014
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#define LTQ_XRX_RCU_RST_STAT_WDT BIT(31)
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/* CPU0 Reset Source Register */
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#define LTQ_FALCON_SYS1_CPU0RS 0x0060
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/* reset cause mask */
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#define LTQ_FALCON_SYS1_CPU0RS_MASK 0x0007
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#define LTQ_FALCON_SYS1_CPU0RS_WDT 0x02
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/*
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* Section 3.4 of the datasheet
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* The password sequence protects the WDT control register from unintended
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* write actions, which might cause malfunction of the WDT.
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*
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* essentially the following two magic passwords need to be written to allow
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* IO access to the WDT core
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*/
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#define LTQ_WDT_CR_PW1 0x00BE0000
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#define LTQ_WDT_CR_PW2 0x00DC0000
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#define LTQ_WDT_CR 0x0 /* watchdog control register */
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#define LTQ_WDT_CR_GEN BIT(31) /* enable bit */
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/* Pre-warning limit set to 1/16 of max WDT period */
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#define LTQ_WDT_CR_PWL (0x3 << 26)
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/* set clock divider to 0x40000 */
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#define LTQ_WDT_CR_CLKDIV (0x3 << 24)
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#define LTQ_WDT_CR_PW_MASK GENMASK(23, 16) /* Password field */
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#define LTQ_WDT_CR_MAX_TIMEOUT ((1 << 16) - 1) /* The reload field is 16 bit */
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#define LTQ_WDT_SR 0x8 /* watchdog status register */
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#define LTQ_WDT_SR_EN BIT(31) /* Enable */
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#define LTQ_WDT_SR_VALUE_MASK GENMASK(15, 0) /* Timer value */
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#define LTQ_WDT_DIVIDER 0x40000
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static bool nowayout = WATCHDOG_NOWAYOUT;
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struct ltq_wdt_hw {
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int (*bootstatus_get)(struct device *dev);
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};
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struct ltq_wdt_priv {
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struct watchdog_device wdt;
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void __iomem *membase;
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unsigned long clk_rate;
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};
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static u32 ltq_wdt_r32(struct ltq_wdt_priv *priv, u32 offset)
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{
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return __raw_readl(priv->membase + offset);
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}
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static void ltq_wdt_w32(struct ltq_wdt_priv *priv, u32 val, u32 offset)
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{
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__raw_writel(val, priv->membase + offset);
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}
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static void ltq_wdt_mask(struct ltq_wdt_priv *priv, u32 clear, u32 set,
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u32 offset)
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{
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u32 val = ltq_wdt_r32(priv, offset);
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val &= ~(clear);
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val |= set;
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ltq_wdt_w32(priv, val, offset);
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}
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static struct ltq_wdt_priv *ltq_wdt_get_priv(struct watchdog_device *wdt)
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{
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return container_of(wdt, struct ltq_wdt_priv, wdt);
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}
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static struct watchdog_info ltq_wdt_info = {
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.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
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WDIOF_CARDRESET,
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.identity = "ltq_wdt",
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};
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static int ltq_wdt_start(struct watchdog_device *wdt)
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{
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struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
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u32 timeout;
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timeout = wdt->timeout * priv->clk_rate;
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ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
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/* write the second magic plus the configuration and new timeout */
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ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
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LTQ_WDT_CR_GEN | LTQ_WDT_CR_PWL | LTQ_WDT_CR_CLKDIV |
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LTQ_WDT_CR_PW2 | timeout,
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LTQ_WDT_CR);
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return 0;
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}
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static int ltq_wdt_stop(struct watchdog_device *wdt)
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{
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struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
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ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
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ltq_wdt_mask(priv, LTQ_WDT_CR_GEN | LTQ_WDT_CR_PW_MASK,
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LTQ_WDT_CR_PW2, LTQ_WDT_CR);
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return 0;
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}
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static int ltq_wdt_ping(struct watchdog_device *wdt)
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{
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struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
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u32 timeout;
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timeout = wdt->timeout * priv->clk_rate;
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ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
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/* write the second magic plus the configuration and new timeout */
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ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
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LTQ_WDT_CR_PW2 | timeout, LTQ_WDT_CR);
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return 0;
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}
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static unsigned int ltq_wdt_get_timeleft(struct watchdog_device *wdt)
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{
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struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
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u64 timeout;
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timeout = ltq_wdt_r32(priv, LTQ_WDT_SR) & LTQ_WDT_SR_VALUE_MASK;
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return do_div(timeout, priv->clk_rate);
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}
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static const struct watchdog_ops ltq_wdt_ops = {
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.owner = THIS_MODULE,
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.start = ltq_wdt_start,
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.stop = ltq_wdt_stop,
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.ping = ltq_wdt_ping,
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.get_timeleft = ltq_wdt_get_timeleft,
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};
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static int ltq_wdt_xrx_bootstatus_get(struct device *dev)
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{
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struct regmap *rcu_regmap;
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u32 val;
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int err;
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rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
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if (IS_ERR(rcu_regmap))
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return PTR_ERR(rcu_regmap);
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err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
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if (err)
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return err;
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if (val & LTQ_XRX_RCU_RST_STAT_WDT)
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return WDIOF_CARDRESET;
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return 0;
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}
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static int ltq_wdt_falcon_bootstatus_get(struct device *dev)
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{
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struct regmap *rcu_regmap;
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u32 val;
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int err;
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rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
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"lantiq,rcu");
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if (IS_ERR(rcu_regmap))
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return PTR_ERR(rcu_regmap);
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err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
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if (err)
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return err;
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if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
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return WDIOF_CARDRESET;
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return 0;
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}
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static int ltq_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ltq_wdt_priv *priv;
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struct watchdog_device *wdt;
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struct clk *clk;
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const struct ltq_wdt_hw *ltq_wdt_hw;
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int ret;
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u32 status;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->membase = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->membase))
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return PTR_ERR(priv->membase);
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/* we do not need to enable the clock as it is always running */
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clk = clk_get_io();
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priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER;
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if (!priv->clk_rate) {
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dev_err(dev, "clock rate less than divider %i\n",
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LTQ_WDT_DIVIDER);
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return -EINVAL;
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}
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wdt = &priv->wdt;
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wdt->info = <q_wdt_info;
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wdt->ops = <q_wdt_ops;
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wdt->min_timeout = 1;
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wdt->max_timeout = LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate;
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wdt->timeout = wdt->max_timeout;
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wdt->parent = dev;
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ltq_wdt_hw = of_device_get_match_data(dev);
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if (ltq_wdt_hw && ltq_wdt_hw->bootstatus_get) {
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ret = ltq_wdt_hw->bootstatus_get(dev);
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if (ret >= 0)
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wdt->bootstatus = ret;
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}
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watchdog_set_nowayout(wdt, nowayout);
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watchdog_init_timeout(wdt, 0, dev);
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status = ltq_wdt_r32(priv, LTQ_WDT_SR);
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if (status & LTQ_WDT_SR_EN) {
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/*
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* If the watchdog is already running overwrite it with our
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* new settings. Stop is not needed as the start call will
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* replace all settings anyway.
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*/
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ltq_wdt_start(wdt);
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set_bit(WDOG_HW_RUNNING, &wdt->status);
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}
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return devm_watchdog_register_device(dev, wdt);
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}
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static const struct ltq_wdt_hw ltq_wdt_xrx100 = {
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.bootstatus_get = ltq_wdt_xrx_bootstatus_get,
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};
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static const struct ltq_wdt_hw ltq_wdt_falcon = {
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.bootstatus_get = ltq_wdt_falcon_bootstatus_get,
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};
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static const struct of_device_id ltq_wdt_match[] = {
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{ .compatible = "lantiq,wdt", .data = NULL },
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{ .compatible = "lantiq,xrx100-wdt", .data = <q_wdt_xrx100 },
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{ .compatible = "lantiq,falcon-wdt", .data = <q_wdt_falcon },
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{},
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};
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MODULE_DEVICE_TABLE(of, ltq_wdt_match);
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static struct platform_driver ltq_wdt_driver = {
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.probe = ltq_wdt_probe,
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.driver = {
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.name = "wdt",
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.of_match_table = ltq_wdt_match,
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},
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};
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module_platform_driver(ltq_wdt_driver);
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
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MODULE_AUTHOR("John Crispin <john@phrozen.org>");
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MODULE_DESCRIPTION("Lantiq SoC Watchdog");
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MODULE_LICENSE("GPL");
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