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f88771ca71
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20190904135918.25352-18-yuehaibing@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
415 lines
9.3 KiB
C
415 lines
9.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// spi-mt7621.c -- MediaTek MT7621 SPI controller driver
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//
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// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
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// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
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// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
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//
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// Some parts are based on spi-orion.c:
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// Author: Shadi Ammouri <shadi@marvell.com>
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// Copyright (C) 2007-2008 Marvell Ltd.
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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#define DRIVER_NAME "spi-mt7621"
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/* in usec */
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#define RALINK_SPI_WAIT_MAX_LOOP 2000
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/* SPISTAT register bit field */
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#define SPISTAT_BUSY BIT(0)
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#define MT7621_SPI_TRANS 0x00
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#define SPITRANS_BUSY BIT(16)
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#define MT7621_SPI_OPCODE 0x04
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#define MT7621_SPI_DATA0 0x08
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#define MT7621_SPI_DATA4 0x18
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#define SPI_CTL_TX_RX_CNT_MASK 0xff
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#define SPI_CTL_START BIT(8)
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#define MT7621_SPI_MASTER 0x28
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#define MASTER_MORE_BUFMODE BIT(2)
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#define MASTER_FULL_DUPLEX BIT(10)
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#define MASTER_RS_CLK_SEL GENMASK(27, 16)
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#define MASTER_RS_CLK_SEL_SHIFT 16
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#define MASTER_RS_SLAVE_SEL GENMASK(31, 29)
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#define MT7621_SPI_MOREBUF 0x2c
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#define MT7621_SPI_POLAR 0x38
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#define MT7621_SPI_SPACE 0x3c
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#define MT7621_CPHA BIT(5)
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#define MT7621_CPOL BIT(4)
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#define MT7621_LSB_FIRST BIT(3)
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struct mt7621_spi {
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struct spi_controller *master;
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void __iomem *base;
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unsigned int sys_freq;
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unsigned int speed;
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struct clk *clk;
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int pending_write;
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};
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static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
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{
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return spi_controller_get_devdata(spi->master);
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}
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static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
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{
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return ioread32(rs->base + reg);
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}
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static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
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{
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iowrite32(val, rs->base + reg);
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}
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static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
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{
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struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
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int cs = spi->chip_select;
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u32 polar = 0;
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u32 master;
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/*
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* Select SPI device 7, enable "more buffer mode" and disable
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* full-duplex (only half-duplex really works on this chip
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* reliably)
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*/
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master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
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master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;
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master &= ~MASTER_FULL_DUPLEX;
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mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
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rs->pending_write = 0;
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if (enable)
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polar = BIT(cs);
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mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
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}
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static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
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{
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struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
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u32 rate;
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u32 reg;
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dev_dbg(&spi->dev, "speed:%u\n", speed);
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rate = DIV_ROUND_UP(rs->sys_freq, speed);
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dev_dbg(&spi->dev, "rate-1:%u\n", rate);
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if (rate > 4097)
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return -EINVAL;
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if (rate < 2)
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rate = 2;
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reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
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reg &= ~MASTER_RS_CLK_SEL;
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reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
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rs->speed = speed;
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reg &= ~MT7621_LSB_FIRST;
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if (spi->mode & SPI_LSB_FIRST)
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reg |= MT7621_LSB_FIRST;
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/*
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* This SPI controller seems to be tested on SPI flash only and some
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* bits are swizzled under other SPI modes probably due to incorrect
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* wiring inside the silicon. Only mode 0 works correctly.
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*/
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reg &= ~(MT7621_CPHA | MT7621_CPOL);
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mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
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return 0;
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}
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static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
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{
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int i;
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for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
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u32 status;
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status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
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if ((status & SPITRANS_BUSY) == 0)
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return 0;
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cpu_relax();
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
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int rx_len, u8 *buf)
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{
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int tx_len;
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/*
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* Combine with any pending write, and perform one or more half-duplex
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* transactions reading 'len' bytes. Data to be written is already in
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* MT7621_SPI_DATA.
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*/
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tx_len = rs->pending_write;
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rs->pending_write = 0;
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while (rx_len || tx_len) {
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int i;
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u32 val = (min(tx_len, 4) * 8) << 24;
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int rx = min(rx_len, 32);
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if (tx_len > 4)
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val |= (tx_len - 4) * 8;
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val |= (rx * 8) << 12;
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mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
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tx_len = 0;
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val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
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val |= SPI_CTL_START;
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mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
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mt7621_spi_wait_till_ready(rs);
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for (i = 0; i < rx; i++) {
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if ((i % 4) == 0)
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val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
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*buf++ = val & 0xff;
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val >>= 8;
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}
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rx_len -= i;
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}
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}
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static inline void mt7621_spi_flush(struct mt7621_spi *rs)
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{
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mt7621_spi_read_half_duplex(rs, 0, NULL);
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}
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static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
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int tx_len, const u8 *buf)
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{
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int len = rs->pending_write;
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int val = 0;
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if (len & 3) {
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val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
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if (len < 4) {
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val <<= (4 - len) * 8;
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val = swab32(val);
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}
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}
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while (tx_len > 0) {
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if (len >= 36) {
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rs->pending_write = len;
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mt7621_spi_flush(rs);
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len = 0;
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}
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val |= *buf++ << (8 * (len & 3));
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len++;
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if ((len & 3) == 0) {
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if (len == 4)
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/* The byte-order of the opcode is weird! */
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val = swab32(val);
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mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
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val = 0;
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}
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tx_len -= 1;
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}
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if (len & 3) {
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if (len < 4) {
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val = swab32(val);
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val >>= (4 - len) * 8;
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}
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mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
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}
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rs->pending_write = len;
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}
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static int mt7621_spi_transfer_one_message(struct spi_controller *master,
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struct spi_message *m)
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{
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struct mt7621_spi *rs = spi_controller_get_devdata(master);
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struct spi_device *spi = m->spi;
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unsigned int speed = spi->max_speed_hz;
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struct spi_transfer *t = NULL;
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int status = 0;
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mt7621_spi_wait_till_ready(rs);
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list_for_each_entry(t, &m->transfers, transfer_list)
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if (t->speed_hz < speed)
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speed = t->speed_hz;
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if (mt7621_spi_prepare(spi, speed)) {
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status = -EIO;
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goto msg_done;
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}
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/* Assert CS */
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mt7621_spi_set_cs(spi, 1);
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m->actual_length = 0;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if ((t->rx_buf) && (t->tx_buf)) {
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/*
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* This controller will shift some extra data out
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* of spi_opcode if (mosi_bit_cnt > 0) &&
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* (cmd_bit_cnt == 0). So the claimed full-duplex
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* support is broken since we have no way to read
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* the MISO value during that bit.
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*/
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status = -EIO;
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goto msg_done;
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} else if (t->rx_buf) {
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mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
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} else if (t->tx_buf) {
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mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
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}
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m->actual_length += t->len;
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}
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/* Flush data and deassert CS */
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mt7621_spi_flush(rs);
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mt7621_spi_set_cs(spi, 0);
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msg_done:
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m->status = status;
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spi_finalize_current_message(master);
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return 0;
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}
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static int mt7621_spi_setup(struct spi_device *spi)
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{
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struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
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if ((spi->max_speed_hz == 0) ||
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(spi->max_speed_hz > (rs->sys_freq / 2)))
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spi->max_speed_hz = rs->sys_freq / 2;
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if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
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dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
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spi->max_speed_hz);
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return -EINVAL;
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}
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return 0;
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}
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static const struct of_device_id mt7621_spi_match[] = {
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{ .compatible = "ralink,mt7621-spi" },
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{},
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};
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MODULE_DEVICE_TABLE(of, mt7621_spi_match);
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static int mt7621_spi_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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struct spi_controller *master;
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struct mt7621_spi *rs;
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void __iomem *base;
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int status = 0;
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struct clk *clk;
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int ret;
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match = of_match_device(mt7621_spi_match, &pdev->dev);
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if (!match)
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return -EINVAL;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
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status);
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return PTR_ERR(clk);
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}
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status = clk_prepare_enable(clk);
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if (status)
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return status;
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master = spi_alloc_master(&pdev->dev, sizeof(*rs));
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if (!master) {
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dev_info(&pdev->dev, "master allocation failed\n");
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return -ENOMEM;
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}
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master->mode_bits = SPI_LSB_FIRST;
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master->flags = SPI_CONTROLLER_HALF_DUPLEX;
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master->setup = mt7621_spi_setup;
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master->transfer_one_message = mt7621_spi_transfer_one_message;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->dev.of_node = pdev->dev.of_node;
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master->num_chipselect = 2;
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dev_set_drvdata(&pdev->dev, master);
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rs = spi_controller_get_devdata(master);
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rs->base = base;
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rs->clk = clk;
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rs->master = master;
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rs->sys_freq = clk_get_rate(rs->clk);
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rs->pending_write = 0;
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dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
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ret = device_reset(&pdev->dev);
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if (ret) {
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dev_err(&pdev->dev, "SPI reset failed!\n");
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return ret;
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}
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return devm_spi_register_controller(&pdev->dev, master);
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}
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static int mt7621_spi_remove(struct platform_device *pdev)
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{
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struct spi_controller *master;
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struct mt7621_spi *rs;
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master = dev_get_drvdata(&pdev->dev);
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rs = spi_controller_get_devdata(master);
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clk_disable_unprepare(rs->clk);
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return 0;
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}
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MODULE_ALIAS("platform:" DRIVER_NAME);
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static struct platform_driver mt7621_spi_driver = {
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.driver = {
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.name = DRIVER_NAME,
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.of_match_table = mt7621_spi_match,
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},
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.probe = mt7621_spi_probe,
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.remove = mt7621_spi_remove,
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};
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module_platform_driver(mt7621_spi_driver);
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MODULE_DESCRIPTION("MT7621 SPI driver");
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MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
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MODULE_LICENSE("GPL");
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