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7cb88afb42
This patch fixes checkpatch error "foo * bar" should be "foo *bar" Signed-off-by: Aishwarya R <aishwaryarj100@gmail.com> Link: https://lore.kernel.org/r/20200407122855.5531-1-aishwaryarj100@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
857 lines
21 KiB
C
857 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Freescale SPI controller driver.
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*
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* Maintainer: Kumar Gala
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*
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* Copyright (C) 2006 Polycom, Inc.
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* CPM SPI and QE buffer descriptors mode support:
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* Copyright (c) 2009 MontaVista Software, Inc.
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* GRLIB support:
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* Copyright (c) 2012 Aeroflex Gaisler AB.
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* Author: Andreas Larsson <andreas@gaisler.com>
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*/
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/fsl_devices.h>
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#include <linux/gpio/consumer.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/types.h>
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#ifdef CONFIG_FSL_SOC
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#include <sysdev/fsl_soc.h>
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#endif
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/* Specific to the MPC8306/MPC8309 */
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#define IMMR_SPI_CS_OFFSET 0x14c
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#define SPI_BOOT_SEL_BIT 0x80000000
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#include "spi-fsl-lib.h"
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#include "spi-fsl-cpm.h"
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#include "spi-fsl-spi.h"
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#define TYPE_FSL 0
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#define TYPE_GRLIB 1
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struct fsl_spi_match_data {
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int type;
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};
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static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
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.type = TYPE_FSL,
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};
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static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
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.type = TYPE_GRLIB,
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};
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static const struct of_device_id of_fsl_spi_match[] = {
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{
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.compatible = "fsl,spi",
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.data = &of_fsl_spi_fsl_config,
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},
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{
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.compatible = "aeroflexgaisler,spictrl",
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.data = &of_fsl_spi_grlib_config,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
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static int fsl_spi_get_type(struct device *dev)
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{
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const struct of_device_id *match;
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if (dev->of_node) {
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match = of_match_node(of_fsl_spi_match, dev->of_node);
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if (match && match->data)
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return ((struct fsl_spi_match_data *)match->data)->type;
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}
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return TYPE_FSL;
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}
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static void fsl_spi_change_mode(struct spi_device *spi)
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{
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struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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struct fsl_spi_reg *reg_base = mspi->reg_base;
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__be32 __iomem *mode = ®_base->mode;
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unsigned long flags;
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if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
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return;
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/* Turn off IRQs locally to minimize time that SPI is disabled. */
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local_irq_save(flags);
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/* Turn off SPI unit prior changing mode */
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mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
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/* When in CPM mode, we need to reinit tx and rx. */
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if (mspi->flags & SPI_CPM_MODE) {
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fsl_spi_cpm_reinit_txrx(mspi);
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}
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mpc8xxx_spi_write_reg(mode, cs->hw_mode);
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local_irq_restore(flags);
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}
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static void fsl_spi_chipselect(struct spi_device *spi, int value)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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struct fsl_spi_platform_data *pdata;
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bool pol = spi->mode & SPI_CS_HIGH;
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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pdata = spi->dev.parent->parent->platform_data;
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if (value == BITBANG_CS_INACTIVE) {
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if (pdata->cs_control)
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pdata->cs_control(spi, !pol);
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}
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if (value == BITBANG_CS_ACTIVE) {
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mpc8xxx_spi->rx_shift = cs->rx_shift;
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mpc8xxx_spi->tx_shift = cs->tx_shift;
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mpc8xxx_spi->get_rx = cs->get_rx;
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mpc8xxx_spi->get_tx = cs->get_tx;
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fsl_spi_change_mode(spi);
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if (pdata->cs_control)
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pdata->cs_control(spi, pol);
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}
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}
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static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
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int bits_per_word, int msb_first)
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{
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*rx_shift = 0;
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*tx_shift = 0;
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if (msb_first) {
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if (bits_per_word <= 8) {
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*rx_shift = 16;
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*tx_shift = 24;
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} else if (bits_per_word <= 16) {
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*rx_shift = 16;
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*tx_shift = 16;
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}
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} else {
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if (bits_per_word <= 8)
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*rx_shift = 8;
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}
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}
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static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
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int bits_per_word, int msb_first)
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{
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*rx_shift = 0;
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*tx_shift = 0;
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if (bits_per_word <= 16) {
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if (msb_first) {
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*rx_shift = 16; /* LSB in bit 16 */
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*tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
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} else {
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*rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
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}
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}
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}
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static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
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struct spi_device *spi,
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struct mpc8xxx_spi *mpc8xxx_spi,
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int bits_per_word)
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{
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cs->rx_shift = 0;
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cs->tx_shift = 0;
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if (bits_per_word <= 8) {
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cs->get_rx = mpc8xxx_spi_rx_buf_u8;
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cs->get_tx = mpc8xxx_spi_tx_buf_u8;
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} else if (bits_per_word <= 16) {
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cs->get_rx = mpc8xxx_spi_rx_buf_u16;
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cs->get_tx = mpc8xxx_spi_tx_buf_u16;
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} else if (bits_per_word <= 32) {
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cs->get_rx = mpc8xxx_spi_rx_buf_u32;
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cs->get_tx = mpc8xxx_spi_tx_buf_u32;
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} else
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return -EINVAL;
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if (mpc8xxx_spi->set_shifts)
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mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
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bits_per_word,
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!(spi->mode & SPI_LSB_FIRST));
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mpc8xxx_spi->rx_shift = cs->rx_shift;
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mpc8xxx_spi->tx_shift = cs->tx_shift;
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mpc8xxx_spi->get_rx = cs->get_rx;
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mpc8xxx_spi->get_tx = cs->get_tx;
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return bits_per_word;
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}
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static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
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struct spi_device *spi,
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int bits_per_word)
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{
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/* QE uses Little Endian for words > 8
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* so transform all words > 8 into 8 bits
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* Unfortnatly that doesn't work for LSB so
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* reject these for now */
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/* Note: 32 bits word, LSB works iff
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* tfcr/rfcr is set to CPMFCR_GBL */
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if (spi->mode & SPI_LSB_FIRST &&
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bits_per_word > 8)
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return -EINVAL;
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if (bits_per_word > 8)
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return 8; /* pretend its 8 bits */
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return bits_per_word;
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}
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static int fsl_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct mpc8xxx_spi *mpc8xxx_spi;
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int bits_per_word = 0;
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u8 pm;
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u32 hz = 0;
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struct spi_mpc8xxx_cs *cs = spi->controller_state;
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mpc8xxx_spi = spi_master_get_devdata(spi->master);
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if (t) {
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bits_per_word = t->bits_per_word;
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hz = t->speed_hz;
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}
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/* spi_transfer level calls that work per-word */
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if (!bits_per_word)
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bits_per_word = spi->bits_per_word;
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if (!hz)
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hz = spi->max_speed_hz;
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if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
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bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
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mpc8xxx_spi,
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bits_per_word);
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else if (mpc8xxx_spi->flags & SPI_QE)
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bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
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bits_per_word);
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if (bits_per_word < 0)
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return bits_per_word;
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if (bits_per_word == 32)
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bits_per_word = 0;
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else
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bits_per_word = bits_per_word - 1;
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/* mask out bits we are going to set */
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cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
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| SPMODE_PM(0xF));
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cs->hw_mode |= SPMODE_LEN(bits_per_word);
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if ((mpc8xxx_spi->spibrg / hz) > 64) {
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cs->hw_mode |= SPMODE_DIV16;
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pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
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WARN_ONCE(pm > 16,
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"%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
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dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
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if (pm > 16)
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pm = 16;
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} else {
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pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
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}
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if (pm)
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pm--;
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cs->hw_mode |= SPMODE_PM(pm);
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fsl_spi_change_mode(spi);
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return 0;
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}
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static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
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struct spi_transfer *t, unsigned int len)
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{
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u32 word;
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struct fsl_spi_reg *reg_base = mspi->reg_base;
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mspi->count = len;
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/* enable rx ints */
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mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
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/* transmit word */
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word = mspi->get_tx(mspi);
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mpc8xxx_spi_write_reg(®_base->transmit, word);
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return 0;
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}
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static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
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bool is_dma_mapped)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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struct fsl_spi_reg *reg_base;
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unsigned int len = t->len;
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u8 bits_per_word;
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int ret;
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reg_base = mpc8xxx_spi->reg_base;
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bits_per_word = spi->bits_per_word;
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if (t->bits_per_word)
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bits_per_word = t->bits_per_word;
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if (bits_per_word > 8) {
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/* invalid length? */
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if (len & 1)
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return -EINVAL;
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len /= 2;
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}
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if (bits_per_word > 16) {
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/* invalid length? */
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if (len & 1)
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return -EINVAL;
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len /= 2;
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}
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mpc8xxx_spi->tx = t->tx_buf;
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mpc8xxx_spi->rx = t->rx_buf;
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reinit_completion(&mpc8xxx_spi->done);
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if (mpc8xxx_spi->flags & SPI_CPM_MODE)
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ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
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else
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ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
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if (ret)
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return ret;
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wait_for_completion(&mpc8xxx_spi->done);
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/* disable rx ints */
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mpc8xxx_spi_write_reg(®_base->mask, 0);
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if (mpc8xxx_spi->flags & SPI_CPM_MODE)
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fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
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return mpc8xxx_spi->count;
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}
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static int fsl_spi_do_one_msg(struct spi_master *master,
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struct spi_message *m)
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{
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struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
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struct spi_device *spi = m->spi;
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struct spi_transfer *t, *first;
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unsigned int cs_change;
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const int nsecs = 50;
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int status, last_bpw;
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/*
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* In CPU mode, optimize large byte transfers to use larger
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* bits_per_word values to reduce number of interrupts taken.
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*/
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if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (t->len < 256 || t->bits_per_word != 8)
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continue;
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if ((t->len & 3) == 0)
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t->bits_per_word = 32;
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else if ((t->len & 1) == 0)
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t->bits_per_word = 16;
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}
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}
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/* Don't allow changes if CS is active */
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cs_change = 1;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (cs_change)
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first = t;
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cs_change = t->cs_change;
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if (first->speed_hz != t->speed_hz) {
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dev_err(&spi->dev,
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"speed_hz cannot change while CS is active\n");
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return -EINVAL;
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}
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}
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last_bpw = -1;
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cs_change = 1;
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status = -EINVAL;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (cs_change || last_bpw != t->bits_per_word)
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status = fsl_spi_setup_transfer(spi, t);
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if (status < 0)
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break;
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last_bpw = t->bits_per_word;
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if (cs_change) {
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fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
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ndelay(nsecs);
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}
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cs_change = t->cs_change;
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if (t->len)
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status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
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if (status) {
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status = -EMSGSIZE;
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break;
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}
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m->actual_length += t->len;
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spi_transfer_delay_exec(t);
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if (cs_change) {
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ndelay(nsecs);
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fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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ndelay(nsecs);
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}
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}
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m->status = status;
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if (status || !cs_change) {
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ndelay(nsecs);
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fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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}
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fsl_spi_setup_transfer(spi, NULL);
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spi_finalize_current_message(master);
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return 0;
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}
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static int fsl_spi_setup(struct spi_device *spi)
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{
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struct mpc8xxx_spi *mpc8xxx_spi;
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struct fsl_spi_reg *reg_base;
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int retval;
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u32 hw_mode;
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struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
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if (!spi->max_speed_hz)
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return -EINVAL;
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if (!cs) {
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cs = kzalloc(sizeof(*cs), GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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spi_set_ctldata(spi, cs);
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}
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mpc8xxx_spi = spi_master_get_devdata(spi->master);
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reg_base = mpc8xxx_spi->reg_base;
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hw_mode = cs->hw_mode; /* Save original settings */
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cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode);
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/* mask out bits we are going to set */
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cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
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| SPMODE_REV | SPMODE_LOOP);
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if (spi->mode & SPI_CPHA)
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cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
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if (spi->mode & SPI_CPOL)
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cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
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if (!(spi->mode & SPI_LSB_FIRST))
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cs->hw_mode |= SPMODE_REV;
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if (spi->mode & SPI_LOOP)
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cs->hw_mode |= SPMODE_LOOP;
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retval = fsl_spi_setup_transfer(spi, NULL);
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if (retval < 0) {
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cs->hw_mode = hw_mode; /* Restore settings */
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return retval;
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}
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/* Initialize chipselect - might be active for SPI_CS_HIGH mode */
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|
fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void fsl_spi_cleanup(struct spi_device *spi)
|
|
{
|
|
struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
|
|
|
|
kfree(cs);
|
|
spi_set_ctldata(spi, NULL);
|
|
}
|
|
|
|
static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
|
|
{
|
|
struct fsl_spi_reg *reg_base = mspi->reg_base;
|
|
|
|
/* We need handle RX first */
|
|
if (events & SPIE_NE) {
|
|
u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
|
|
|
|
if (mspi->rx)
|
|
mspi->get_rx(rx_data, mspi);
|
|
}
|
|
|
|
if ((events & SPIE_NF) == 0)
|
|
/* spin until TX is done */
|
|
while (((events =
|
|
mpc8xxx_spi_read_reg(®_base->event)) &
|
|
SPIE_NF) == 0)
|
|
cpu_relax();
|
|
|
|
/* Clear the events */
|
|
mpc8xxx_spi_write_reg(®_base->event, events);
|
|
|
|
mspi->count -= 1;
|
|
if (mspi->count) {
|
|
u32 word = mspi->get_tx(mspi);
|
|
|
|
mpc8xxx_spi_write_reg(®_base->transmit, word);
|
|
} else {
|
|
complete(&mspi->done);
|
|
}
|
|
}
|
|
|
|
static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
|
|
{
|
|
struct mpc8xxx_spi *mspi = context_data;
|
|
irqreturn_t ret = IRQ_NONE;
|
|
u32 events;
|
|
struct fsl_spi_reg *reg_base = mspi->reg_base;
|
|
|
|
/* Get interrupt events(tx/rx) */
|
|
events = mpc8xxx_spi_read_reg(®_base->event);
|
|
if (events)
|
|
ret = IRQ_HANDLED;
|
|
|
|
dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
|
|
|
|
if (mspi->flags & SPI_CPM_MODE)
|
|
fsl_spi_cpm_irq(mspi, events);
|
|
else
|
|
fsl_spi_cpu_irq(mspi, events);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
|
|
{
|
|
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
|
|
struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
|
|
u32 slvsel;
|
|
u16 cs = spi->chip_select;
|
|
|
|
if (spi->cs_gpiod) {
|
|
gpiod_set_value(spi->cs_gpiod, on);
|
|
} else if (cs < mpc8xxx_spi->native_chipselects) {
|
|
slvsel = mpc8xxx_spi_read_reg(®_base->slvsel);
|
|
slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
|
|
mpc8xxx_spi_write_reg(®_base->slvsel, slvsel);
|
|
}
|
|
}
|
|
|
|
static void fsl_spi_grlib_probe(struct device *dev)
|
|
{
|
|
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
|
|
struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
|
|
int mbits;
|
|
u32 capabilities;
|
|
|
|
capabilities = mpc8xxx_spi_read_reg(®_base->cap);
|
|
|
|
mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
|
|
mbits = SPCAP_MAXWLEN(capabilities);
|
|
if (mbits)
|
|
mpc8xxx_spi->max_bits_per_word = mbits + 1;
|
|
|
|
mpc8xxx_spi->native_chipselects = 0;
|
|
if (SPCAP_SSEN(capabilities)) {
|
|
mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
|
|
mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff);
|
|
}
|
|
master->num_chipselect = mpc8xxx_spi->native_chipselects;
|
|
pdata->cs_control = fsl_spi_grlib_cs_control;
|
|
}
|
|
|
|
static struct spi_master *fsl_spi_probe(struct device *dev,
|
|
struct resource *mem, unsigned int irq)
|
|
{
|
|
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
|
|
struct spi_master *master;
|
|
struct mpc8xxx_spi *mpc8xxx_spi;
|
|
struct fsl_spi_reg *reg_base;
|
|
u32 regval;
|
|
int ret = 0;
|
|
|
|
master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
|
|
if (master == NULL) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
dev_set_drvdata(dev, master);
|
|
|
|
mpc8xxx_spi_probe(dev, mem, irq);
|
|
|
|
master->setup = fsl_spi_setup;
|
|
master->cleanup = fsl_spi_cleanup;
|
|
master->transfer_one_message = fsl_spi_do_one_msg;
|
|
master->use_gpio_descriptors = true;
|
|
|
|
mpc8xxx_spi = spi_master_get_devdata(master);
|
|
mpc8xxx_spi->max_bits_per_word = 32;
|
|
mpc8xxx_spi->type = fsl_spi_get_type(dev);
|
|
|
|
ret = fsl_spi_cpm_init(mpc8xxx_spi);
|
|
if (ret)
|
|
goto err_cpm_init;
|
|
|
|
mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
|
|
if (IS_ERR(mpc8xxx_spi->reg_base)) {
|
|
ret = PTR_ERR(mpc8xxx_spi->reg_base);
|
|
goto err_probe;
|
|
}
|
|
|
|
if (mpc8xxx_spi->type == TYPE_GRLIB)
|
|
fsl_spi_grlib_probe(dev);
|
|
|
|
master->bits_per_word_mask =
|
|
(SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
|
|
SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
|
|
|
|
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
|
|
mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
|
|
|
|
if (mpc8xxx_spi->set_shifts)
|
|
/* 8 bits per word and MSB first */
|
|
mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
|
|
&mpc8xxx_spi->tx_shift, 8, 1);
|
|
|
|
/* Register for SPI Interrupt */
|
|
ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
|
|
0, "fsl_spi", mpc8xxx_spi);
|
|
|
|
if (ret != 0)
|
|
goto err_probe;
|
|
|
|
reg_base = mpc8xxx_spi->reg_base;
|
|
|
|
/* SPI controller initializations */
|
|
mpc8xxx_spi_write_reg(®_base->mode, 0);
|
|
mpc8xxx_spi_write_reg(®_base->mask, 0);
|
|
mpc8xxx_spi_write_reg(®_base->command, 0);
|
|
mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
|
|
|
|
/* Enable SPI interface */
|
|
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
|
|
if (mpc8xxx_spi->max_bits_per_word < 8) {
|
|
regval &= ~SPMODE_LEN(0xF);
|
|
regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
|
|
}
|
|
if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
|
|
regval |= SPMODE_OP;
|
|
|
|
mpc8xxx_spi_write_reg(®_base->mode, regval);
|
|
|
|
ret = devm_spi_register_master(dev, master);
|
|
if (ret < 0)
|
|
goto err_probe;
|
|
|
|
dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
|
|
mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
|
|
|
|
return master;
|
|
|
|
err_probe:
|
|
fsl_spi_cpm_free(mpc8xxx_spi);
|
|
err_cpm_init:
|
|
spi_master_put(master);
|
|
err:
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
static void fsl_spi_cs_control(struct spi_device *spi, bool on)
|
|
{
|
|
if (spi->cs_gpiod) {
|
|
gpiod_set_value(spi->cs_gpiod, on);
|
|
} else {
|
|
struct device *dev = spi->dev.parent->parent;
|
|
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
|
|
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
|
|
|
|
if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
|
|
return;
|
|
iowrite32be(on ? SPI_BOOT_SEL_BIT : 0, pinfo->immr_spi_cs);
|
|
}
|
|
}
|
|
|
|
static int of_fsl_spi_probe(struct platform_device *ofdev)
|
|
{
|
|
struct device *dev = &ofdev->dev;
|
|
struct device_node *np = ofdev->dev.of_node;
|
|
struct spi_master *master;
|
|
struct resource mem;
|
|
int irq, type;
|
|
int ret;
|
|
|
|
ret = of_mpc8xxx_spi_probe(ofdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
type = fsl_spi_get_type(&ofdev->dev);
|
|
if (type == TYPE_FSL) {
|
|
struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
|
|
#if IS_ENABLED(CONFIG_FSL_SOC)
|
|
struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
|
|
bool spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
|
|
|
|
if (spisel_boot) {
|
|
pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
|
|
if (!pinfo->immr_spi_cs)
|
|
return -ENOMEM;
|
|
}
|
|
#endif
|
|
/*
|
|
* Handle the case where we have one hardwired (always selected)
|
|
* device on the first "chipselect". Else we let the core code
|
|
* handle any GPIOs or native chip selects and assign the
|
|
* appropriate callback for dealing with the CS lines. This isn't
|
|
* supported on the GRLIB variant.
|
|
*/
|
|
ret = gpiod_count(dev, "cs");
|
|
if (ret <= 0)
|
|
pdata->max_chipselect = 1;
|
|
else
|
|
pdata->cs_control = fsl_spi_cs_control;
|
|
}
|
|
|
|
ret = of_address_to_resource(np, 0, &mem);
|
|
if (ret)
|
|
return ret;
|
|
|
|
irq = platform_get_irq(ofdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
master = fsl_spi_probe(dev, &mem, irq);
|
|
|
|
return PTR_ERR_OR_ZERO(master);
|
|
}
|
|
|
|
static int of_fsl_spi_remove(struct platform_device *ofdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(ofdev);
|
|
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
|
|
|
|
fsl_spi_cpm_free(mpc8xxx_spi);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver of_fsl_spi_driver = {
|
|
.driver = {
|
|
.name = "fsl_spi",
|
|
.of_match_table = of_fsl_spi_match,
|
|
},
|
|
.probe = of_fsl_spi_probe,
|
|
.remove = of_fsl_spi_remove,
|
|
};
|
|
|
|
#ifdef CONFIG_MPC832x_RDB
|
|
/*
|
|
* XXX XXX XXX
|
|
* This is "legacy" platform driver, was used by the MPC8323E-RDB boards
|
|
* only. The driver should go away soon, since newer MPC8323E-RDB's device
|
|
* tree can work with OpenFirmware driver. But for now we support old trees
|
|
* as well.
|
|
*/
|
|
static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *mem;
|
|
int irq;
|
|
struct spi_master *master;
|
|
|
|
if (!dev_get_platdata(&pdev->dev))
|
|
return -EINVAL;
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!mem)
|
|
return -EINVAL;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq <= 0)
|
|
return -EINVAL;
|
|
|
|
master = fsl_spi_probe(&pdev->dev, mem, irq);
|
|
return PTR_ERR_OR_ZERO(master);
|
|
}
|
|
|
|
static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
|
|
|
|
fsl_spi_cpm_free(mpc8xxx_spi);
|
|
|
|
return 0;
|
|
}
|
|
|
|
MODULE_ALIAS("platform:mpc8xxx_spi");
|
|
static struct platform_driver mpc8xxx_spi_driver = {
|
|
.probe = plat_mpc8xxx_spi_probe,
|
|
.remove = plat_mpc8xxx_spi_remove,
|
|
.driver = {
|
|
.name = "mpc8xxx_spi",
|
|
},
|
|
};
|
|
|
|
static bool legacy_driver_failed;
|
|
|
|
static void __init legacy_driver_register(void)
|
|
{
|
|
legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
|
|
}
|
|
|
|
static void __exit legacy_driver_unregister(void)
|
|
{
|
|
if (legacy_driver_failed)
|
|
return;
|
|
platform_driver_unregister(&mpc8xxx_spi_driver);
|
|
}
|
|
#else
|
|
static void __init legacy_driver_register(void) {}
|
|
static void __exit legacy_driver_unregister(void) {}
|
|
#endif /* CONFIG_MPC832x_RDB */
|
|
|
|
static int __init fsl_spi_init(void)
|
|
{
|
|
legacy_driver_register();
|
|
return platform_driver_register(&of_fsl_spi_driver);
|
|
}
|
|
module_init(fsl_spi_init);
|
|
|
|
static void __exit fsl_spi_exit(void)
|
|
{
|
|
platform_driver_unregister(&of_fsl_spi_driver);
|
|
legacy_driver_unregister();
|
|
}
|
|
module_exit(fsl_spi_exit);
|
|
|
|
MODULE_AUTHOR("Kumar Gala");
|
|
MODULE_DESCRIPTION("Simple Freescale SPI Driver");
|
|
MODULE_LICENSE("GPL");
|