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Since from now the former Intel MID platform layer is used as a generic DW SPI DMA module, let's alter the internal methods naming to be DMA-related instead of having the "mid_" prefix. Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Feng Tang <feng.tang@intel.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20200529131205.31838-14-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
220 lines
5.0 KiB
C
220 lines
5.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* PCI interface driver for DW SPI Core
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*
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* Copyright (c) 2009, 2014 Intel Corporation.
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*/
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#include <linux/pci.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/module.h>
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#include "spi-dw.h"
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#define DRIVER_NAME "dw_spi_pci"
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/* HW info for MRST Clk Control Unit, 32b reg per controller */
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#define MRST_SPI_CLK_BASE 100000000 /* 100m */
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#define MRST_CLK_SPI_REG 0xff11d86c
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#define CLK_SPI_BDIV_OFFSET 0
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#define CLK_SPI_BDIV_MASK 0x00000007
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#define CLK_SPI_CDIV_OFFSET 9
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#define CLK_SPI_CDIV_MASK 0x00000e00
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#define CLK_SPI_DISABLE_OFFSET 8
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struct spi_pci_desc {
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int (*setup)(struct dw_spi *);
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u16 num_cs;
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u16 bus_num;
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u32 max_freq;
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};
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static int spi_mid_init(struct dw_spi *dws)
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{
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void __iomem *clk_reg;
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u32 clk_cdiv;
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clk_reg = ioremap(MRST_CLK_SPI_REG, 16);
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if (!clk_reg)
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return -ENOMEM;
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/* Get SPI controller operating freq info */
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clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
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clk_cdiv &= CLK_SPI_CDIV_MASK;
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clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
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dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
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iounmap(clk_reg);
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/* Register hook to configure CTRLR0 */
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dws->update_cr0 = dw_spi_update_cr0;
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dw_spi_dma_setup_mfld(dws);
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return 0;
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}
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static int spi_generic_init(struct dw_spi *dws)
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{
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/* Register hook to configure CTRLR0 */
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dws->update_cr0 = dw_spi_update_cr0;
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dw_spi_dma_setup_generic(dws);
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return 0;
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}
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static struct spi_pci_desc spi_pci_mid_desc_1 = {
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.setup = spi_mid_init,
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.num_cs = 5,
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.bus_num = 0,
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};
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static struct spi_pci_desc spi_pci_mid_desc_2 = {
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.setup = spi_mid_init,
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.num_cs = 2,
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.bus_num = 1,
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};
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static struct spi_pci_desc spi_pci_ehl_desc = {
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.setup = spi_generic_init,
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.num_cs = 2,
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.bus_num = -1,
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.max_freq = 100000000,
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};
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static int spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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struct dw_spi *dws;
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struct spi_pci_desc *desc = (struct spi_pci_desc *)ent->driver_data;
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int pci_bar = 0;
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int ret;
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ret = pcim_enable_device(pdev);
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if (ret)
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return ret;
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dws = devm_kzalloc(&pdev->dev, sizeof(*dws), GFP_KERNEL);
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if (!dws)
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return -ENOMEM;
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/* Get basic io resource and map it */
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dws->paddr = pci_resource_start(pdev, pci_bar);
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pci_set_master(pdev);
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ret = pcim_iomap_regions(pdev, 1 << pci_bar, pci_name(pdev));
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if (ret)
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return ret;
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ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
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if (ret < 0)
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return ret;
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dws->regs = pcim_iomap_table(pdev)[pci_bar];
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dws->irq = pci_irq_vector(pdev, 0);
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/*
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* Specific handling for platforms, like dma setup,
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* clock rate, FIFO depth.
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*/
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if (desc) {
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dws->num_cs = desc->num_cs;
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dws->bus_num = desc->bus_num;
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dws->max_freq = desc->max_freq;
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if (desc->setup) {
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ret = desc->setup(dws);
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if (ret)
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return ret;
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}
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} else {
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pci_free_irq_vectors(pdev);
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return -ENODEV;
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}
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ret = dw_spi_add_host(&pdev->dev, dws);
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if (ret) {
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pci_free_irq_vectors(pdev);
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return ret;
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}
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/* PCI hook and SPI hook use the same drv data */
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pci_set_drvdata(pdev, dws);
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dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n",
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pdev->vendor, pdev->device);
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pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_runtime_put_autosuspend(&pdev->dev);
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pm_runtime_allow(&pdev->dev);
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return 0;
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}
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static void spi_pci_remove(struct pci_dev *pdev)
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{
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struct dw_spi *dws = pci_get_drvdata(pdev);
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pm_runtime_forbid(&pdev->dev);
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pm_runtime_get_noresume(&pdev->dev);
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dw_spi_remove_host(dws);
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pci_free_irq_vectors(pdev);
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}
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#ifdef CONFIG_PM_SLEEP
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static int spi_suspend(struct device *dev)
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{
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struct dw_spi *dws = dev_get_drvdata(dev);
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return dw_spi_suspend_host(dws);
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}
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static int spi_resume(struct device *dev)
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{
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struct dw_spi *dws = dev_get_drvdata(dev);
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return dw_spi_resume_host(dws);
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}
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#endif
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static SIMPLE_DEV_PM_OPS(dw_spi_pm_ops, spi_suspend, spi_resume);
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static const struct pci_device_id pci_ids[] = {
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/* Intel MID platform SPI controller 0 */
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/*
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* The access to the device 8086:0801 is disabled by HW, since it's
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* exclusively used by SCU to communicate with MSIC.
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*/
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/* Intel MID platform SPI controller 1 */
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{ PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&spi_pci_mid_desc_1},
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/* Intel MID platform SPI controller 2 */
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{ PCI_VDEVICE(INTEL, 0x0812), (kernel_ulong_t)&spi_pci_mid_desc_2},
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/* Intel Elkhart Lake PSE SPI controllers */
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{ PCI_VDEVICE(INTEL, 0x4b84), (kernel_ulong_t)&spi_pci_ehl_desc},
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{ PCI_VDEVICE(INTEL, 0x4b85), (kernel_ulong_t)&spi_pci_ehl_desc},
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{ PCI_VDEVICE(INTEL, 0x4b86), (kernel_ulong_t)&spi_pci_ehl_desc},
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{ PCI_VDEVICE(INTEL, 0x4b87), (kernel_ulong_t)&spi_pci_ehl_desc},
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{},
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};
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MODULE_DEVICE_TABLE(pci, pci_ids);
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static struct pci_driver dw_spi_driver = {
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.name = DRIVER_NAME,
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.id_table = pci_ids,
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.probe = spi_pci_probe,
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.remove = spi_pci_remove,
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.driver = {
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.pm = &dw_spi_pm_ops,
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},
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};
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module_pci_driver(dw_spi_driver);
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MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
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MODULE_DESCRIPTION("PCI interface driver for DW SPI Core");
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MODULE_LICENSE("GPL v2");
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