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08ba93064e
Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW APB SSI devices embedded into the SoC. Currently the DMA-based transfers are supported by the DW APB SPI driver only as a middle layer code for Intel MID/Elkhart PCI devices. Seeing the same code can be used for normal platform DMAC device we introduced a set of patches to fix it within this series. First of all we need to add the Tx and Rx DMA channels support into the DW APB SSI binding. Then there are several fixes and cleanups provided as a initial preparation for the Generic DMA support integration: add Tx/Rx finish wait methods, clear DMAC register when done or stopped, Fix native CS being unset, enable interrupts in accordance with DMA xfer mode, discard static DW DMA slave structures, discard unused void priv pointer and dma_width member of the dw_spi structure, provide the DMA Tx/Rx burst length parametrisation and make sure it's optionally set in accordance with the DMA max-burst capability. In order to have the DW APB SSI MMIO driver working with DMA we need to initialize the paddr field with the physical base address of the DW APB SSI registers space. Then we unpin the Intel MID specific code from the generic DMA one and placed it into the spi-dw-pci.c driver, which is a better place for it anyway. After that the naming cleanups are performed since the code is going to be used for a generic DMAC device. Finally the Generic DMA initialization can be added to the generic version of the DW APB SSI IP. Last but not least we traditionally convert the legacy plain text-based dt-binding file with yaml-based one and as a cherry on a cake replace the manually written DebugFS registers read method with a ready-to-use for the same purpose regset32 DebugFS interface usage. This patchset is rebased and tested on the spi/for-next (5.7-rc5): base-commit: fe9fce6b2cf3 ("Merge remote-tracking branch 'spi/for-5.8' into spi-next") Link: https://lore.kernel.org/linux-spi/20200508132943.9826-1-Sergey.Semin@baikalelectronics.ru/ Changelog v2: - Rebase on top of the spi repository for-next branch. - Move bindings conversion patch to the tail of the series. - Move fixes to the head of the series. - Apply as many changes as possible to be applied the Generic DMA functionality support is added and the spi-dw-mid is moved to the spi-dw-dma driver. - Discard patch "spi: dw: Fix dma_slave_config used partly uninitialized" since the problem has already been fixed. - Add new patch "spi: dw: Discard unused void priv pointer". - Add new patch "spi: dw: Discard dma_width member of the dw_spi structure". n_bytes member of the DW SPI data can be used instead. - Build the DMA functionality into the DW APB SSI core if required instead of creating a separate kernel module. - Use conditional statement instead of the ternary operator in the ref clock getter. Link: https://lore.kernel.org/linux-spi/20200515104758.6934-1-Sergey.Semin@baikalelectronics.ru/ Changelog v3: - Use spi_delay_exec() method to wait for the DMA operation completion. - Explicitly initialize the dw_dma_slave members on stack. - Discard the dws->fifo_len utilization in the Tx FIFO DMA threshold setting from the patch where we just add the default burst length constants. - Use min() method to calculate the optimal burst values. - Add new patch which moves the spi-dw.c source file to spi-dw-core.c in order to preserve the DW APB SSI core driver name. - Add commas in the debugfs_reg32 structure initializer and after the last entry of the dw_spi_dbgfs_regs array. Link: https://lore.kernel.org/linux-spi/20200521012206.14472-1-Sergey.Semin@baikalelectronics.ru Changelog v4: - Get back ndelay() method to wait for an SPI transfer completion. spi_delay_exec() isn't suitable for the atomic context. Link: https://lore.kernel.org/linux-spi/20200522000806.7381-1-Sergey.Semin@baikalelectronics.ru Changelog v5: - Refactor the Tx/Rx DMA-based SPI transfers wait methods. - Add a new patch "spi: dw: Set xfer effective_speed_hz". - Add a new patch "spi: dw: Return any value retrieved from the dma_transfer callback" as a preparation patch before implementing the local DMA, Tx SPI and Rx SPI transfers wait methods. - Add a new patch "spi: dw: Locally wait for the DMA transactions completion", which provides a local DMA transaction complete method - Create a dedicated patch which adds the Rx-done wait method: "spi: dw: Add SPI Rx-done wait method to DMA-based transfer". - Add more detailed description of the problems the Tx/Rx-wait methods-related patches fix. - Wait for the SPI Tx and Rx transfers being finished in the mid_spi_dma_transfer() method executed in the task context. - Use spi_delay_exec() to wait for the SPI Tx/Rx completion, since now the driver calls the wait methods in the kernel thread context. - Use SPI_DELAY_UNIT_SCK spi_delay unit for Tx-wait delay, since SPI xfer's are now have the effective_speed_hz initialized. - Rx-wait for a delay correlated with the APB/SSI synchronous clock rate instead of using the SPI bus clock rate. Link: https://lore.kernel.org/linux-spi/20200529035915.20790-1-Sergey.Semin@baikalelectronics.ru Changelog v6: - Provide a more detailed description of the patch: 2901db35bea1 ("spi: dw: Locally wait for the DMA transfers completion") - Calculate the Rx delay with better accuracy by moving 4-multiplication to the head of the formulae: ns = 4U * NSEC_PER_SEC / dws->max_freq * nents. Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru> Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru> Cc: Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru> Cc: Vadim Vlasov <V.Vlasov@baikalelectronics.ru> Cc: Alexey Kolotnikov <Alexey.Kolotnikov@baikalelectronics.ru> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Feng Tang <feng.tang@intel.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-spi@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Serge Semin (16): spi: dw: Set xfer effective_speed_hz spi: dw: Return any value retrieved from the dma_transfer callback spi: dw: Locally wait for the DMA transfers completion spi: dw: Add SPI Tx-done wait method to DMA-based transfer spi: dw: Add SPI Rx-done wait method to DMA-based transfer spi: dw: Parameterize the DMA Rx/Tx burst length spi: dw: Use DMA max burst to set the request thresholds spi: dw: Fix Rx-only DMA transfers spi: dw: Add core suffix to the DW APB SSI core source file spi: dw: Move Non-DMA code to the DW PCIe-SPI driver spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core spi: dw: Cleanup generic DW DMA code namings spi: dw: Add DMA support to the DW SPI MMIO driver spi: dw: Use regset32 DebugFS method to create regdump file dt-bindings: spi: Convert DW SPI binding to DT schema .../bindings/spi/snps,dw-apb-ssi.txt | 44 -- .../bindings/spi/snps,dw-apb-ssi.yaml | 127 +++++ .../devicetree/bindings/spi/spi-dw.txt | 24 - drivers/spi/Kconfig | 15 +- drivers/spi/Makefile | 5 +- drivers/spi/{spi-dw.c => spi-dw-core.c} | 95 ++-- drivers/spi/spi-dw-dma.c | 482 ++++++++++++++++++ drivers/spi/spi-dw-mid.c | 382 -------------- drivers/spi/spi-dw-mmio.c | 4 + drivers/spi/spi-dw-pci.c | 50 +- drivers/spi/spi-dw.h | 20 +- 11 files changed, 719 insertions(+), 529 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml delete mode 100644 Documentation/devicetree/bindings/spi/spi-dw.txt rename drivers/spi/{spi-dw.c => spi-dw-core.c} (82%) create mode 100644 drivers/spi/spi-dw-dma.c delete mode 100644 drivers/spi/spi-dw-mid.c -- 2.26.2
326 lines
8.4 KiB
C
326 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Memory-mapped interface driver for DW SPI Core
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*
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* Copyright (c) 2010, Octasic semiconductor.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/scatterlist.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/acpi.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "spi-dw.h"
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#define DRIVER_NAME "dw_spi_mmio"
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struct dw_spi_mmio {
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struct dw_spi dws;
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struct clk *clk;
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struct clk *pclk;
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void *priv;
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struct reset_control *rstc;
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};
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#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
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#define OCELOT_IF_SI_OWNER_OFFSET 4
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#define JAGUAR2_IF_SI_OWNER_OFFSET 6
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#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
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#define MSCC_IF_SI_OWNER_SISL 0
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#define MSCC_IF_SI_OWNER_SIBM 1
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#define MSCC_IF_SI_OWNER_SIMC 2
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#define MSCC_SPI_MST_SW_MODE 0x14
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#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
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#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
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/*
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* For Keem Bay, CTRLR0[31] is used to select controller mode.
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* 0: SSI is slave
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* 1: SSI is master
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*/
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#define KEEMBAY_CTRLR0_SSIC_IS_MST BIT(31)
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struct dw_spi_mscc {
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struct regmap *syscon;
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void __iomem *spi_mst;
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};
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/*
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* The Designware SPI controller (referred to as master in the documentation)
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* automatically deasserts chip select when the tx fifo is empty. The chip
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* selects then needs to be either driven as GPIOs or, for the first 4 using the
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* the SPI boot controller registers. the final chip select is an OR gate
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* between the Designware SPI controller and the SPI boot controller.
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*/
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static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
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{
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struct dw_spi *dws = spi_master_get_devdata(spi->master);
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struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
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struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
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u32 cs = spi->chip_select;
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if (cs < 4) {
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u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
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if (!enable)
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sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
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writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
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}
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dw_spi_set_cs(spi, enable);
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}
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static int dw_spi_mscc_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio,
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const char *cpu_syscon, u32 if_si_owner_offset)
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{
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struct dw_spi_mscc *dwsmscc;
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dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
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if (!dwsmscc)
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return -ENOMEM;
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dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(dwsmscc->spi_mst)) {
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dev_err(&pdev->dev, "SPI_MST region map failed\n");
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return PTR_ERR(dwsmscc->spi_mst);
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}
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dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
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if (IS_ERR(dwsmscc->syscon))
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return PTR_ERR(dwsmscc->syscon);
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/* Deassert all CS */
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writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
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/* Select the owner of the SI interface */
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regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
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MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
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MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
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dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
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dwsmmio->priv = dwsmscc;
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/* Register hook to configure CTRLR0 */
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dwsmmio->dws.update_cr0 = dw_spi_update_cr0;
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return 0;
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}
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static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
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OCELOT_IF_SI_OWNER_OFFSET);
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}
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static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
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JAGUAR2_IF_SI_OWNER_OFFSET);
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}
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static int dw_spi_alpine_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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dwsmmio->dws.cs_override = 1;
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/* Register hook to configure CTRLR0 */
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dwsmmio->dws.update_cr0 = dw_spi_update_cr0;
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return 0;
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}
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static int dw_spi_dw_apb_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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/* Register hook to configure CTRLR0 */
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dwsmmio->dws.update_cr0 = dw_spi_update_cr0;
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dw_spi_dma_setup_generic(&dwsmmio->dws);
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return 0;
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}
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static int dw_spi_dwc_ssi_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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/* Register hook to configure CTRLR0 */
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dwsmmio->dws.update_cr0 = dw_spi_update_cr0_v1_01a;
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dw_spi_dma_setup_generic(&dwsmmio->dws);
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return 0;
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}
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static u32 dw_spi_update_cr0_keembay(struct spi_controller *master,
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struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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u32 cr0 = dw_spi_update_cr0_v1_01a(master, spi, transfer);
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return cr0 | KEEMBAY_CTRLR0_SSIC_IS_MST;
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}
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static int dw_spi_keembay_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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/* Register hook to configure CTRLR0 */
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dwsmmio->dws.update_cr0 = dw_spi_update_cr0_keembay;
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return 0;
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}
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static int dw_spi_mmio_probe(struct platform_device *pdev)
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{
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int (*init_func)(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio);
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struct dw_spi_mmio *dwsmmio;
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struct resource *mem;
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struct dw_spi *dws;
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int ret;
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int num_cs;
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dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
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GFP_KERNEL);
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if (!dwsmmio)
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return -ENOMEM;
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dws = &dwsmmio->dws;
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/* Get basic io resource and map it */
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dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
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if (IS_ERR(dws->regs))
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return PTR_ERR(dws->regs);
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dws->paddr = mem->start;
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dws->irq = platform_get_irq(pdev, 0);
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if (dws->irq < 0)
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return dws->irq; /* -ENXIO */
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dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(dwsmmio->clk))
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return PTR_ERR(dwsmmio->clk);
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ret = clk_prepare_enable(dwsmmio->clk);
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if (ret)
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return ret;
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/* Optional clock needed to access the registers */
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dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
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if (IS_ERR(dwsmmio->pclk)) {
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ret = PTR_ERR(dwsmmio->pclk);
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goto out_clk;
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}
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ret = clk_prepare_enable(dwsmmio->pclk);
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if (ret)
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goto out_clk;
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/* find an optional reset controller */
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dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
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if (IS_ERR(dwsmmio->rstc)) {
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ret = PTR_ERR(dwsmmio->rstc);
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goto out_clk;
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}
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reset_control_deassert(dwsmmio->rstc);
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dws->bus_num = pdev->id;
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dws->max_freq = clk_get_rate(dwsmmio->clk);
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device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
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num_cs = 4;
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device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
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dws->num_cs = num_cs;
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init_func = device_get_match_data(&pdev->dev);
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if (init_func) {
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ret = init_func(pdev, dwsmmio);
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if (ret)
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goto out;
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}
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pm_runtime_enable(&pdev->dev);
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ret = dw_spi_add_host(&pdev->dev, dws);
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if (ret)
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goto out;
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platform_set_drvdata(pdev, dwsmmio);
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return 0;
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out:
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pm_runtime_disable(&pdev->dev);
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clk_disable_unprepare(dwsmmio->pclk);
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out_clk:
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clk_disable_unprepare(dwsmmio->clk);
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reset_control_assert(dwsmmio->rstc);
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return ret;
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}
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static int dw_spi_mmio_remove(struct platform_device *pdev)
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{
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struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
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dw_spi_remove_host(&dwsmmio->dws);
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pm_runtime_disable(&pdev->dev);
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clk_disable_unprepare(dwsmmio->pclk);
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clk_disable_unprepare(dwsmmio->clk);
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reset_control_assert(dwsmmio->rstc);
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return 0;
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}
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static const struct of_device_id dw_spi_mmio_of_match[] = {
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{ .compatible = "snps,dw-apb-ssi", .data = dw_spi_dw_apb_init},
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{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
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{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
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{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
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{ .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init},
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{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init},
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{ .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
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{ /* end of table */}
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};
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MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
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#ifdef CONFIG_ACPI
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static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
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{"HISI0173", (kernel_ulong_t)dw_spi_dw_apb_init},
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{},
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};
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MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
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#endif
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static struct platform_driver dw_spi_mmio_driver = {
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.probe = dw_spi_mmio_probe,
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.remove = dw_spi_mmio_remove,
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.driver = {
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.name = DRIVER_NAME,
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.of_match_table = dw_spi_mmio_of_match,
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.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
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},
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};
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module_platform_driver(dw_spi_mmio_driver);
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MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
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MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
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MODULE_LICENSE("GPL v2");
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