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3d7db0f11c
It's better to understand what bits are set for DMA and for IRQ handling in mid_spi_dma_setup() if they are grouped accordingly. Thus, refactor mid_spi_dma_setup() to separate DMA and IRQ configuration. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200529183150.44149-2-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
481 lines
11 KiB
C
481 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Special handling for DW DMA core
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*
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* Copyright (c) 2009, 2014 Intel Corporation.
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*/
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#include <linux/completion.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/irqreturn.h>
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#include <linux/jiffies.h>
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#include <linux/pci.h>
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#include <linux/platform_data/dma-dw.h>
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#include <linux/spi/spi.h>
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#include <linux/types.h>
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#include "spi-dw.h"
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#define WAIT_RETRIES 5
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#define RX_BUSY 0
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#define RX_BURST_LEVEL 16
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#define TX_BUSY 1
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#define TX_BURST_LEVEL 16
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static bool dw_spi_dma_chan_filter(struct dma_chan *chan, void *param)
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{
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struct dw_dma_slave *s = param;
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if (s->dma_dev != chan->device->dev)
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return false;
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chan->private = s;
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return true;
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}
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static void dw_spi_dma_maxburst_init(struct dw_spi *dws)
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{
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struct dma_slave_caps caps;
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u32 max_burst, def_burst;
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int ret;
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def_burst = dws->fifo_len / 2;
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ret = dma_get_slave_caps(dws->rxchan, &caps);
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if (!ret && caps.max_burst)
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max_burst = caps.max_burst;
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else
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max_burst = RX_BURST_LEVEL;
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dws->rxburst = min(max_burst, def_burst);
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ret = dma_get_slave_caps(dws->txchan, &caps);
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if (!ret && caps.max_burst)
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max_burst = caps.max_burst;
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else
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max_burst = TX_BURST_LEVEL;
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dws->txburst = min(max_burst, def_burst);
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}
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static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
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{
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struct dw_dma_slave dma_tx = { .dst_id = 1 }, *tx = &dma_tx;
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struct dw_dma_slave dma_rx = { .src_id = 0 }, *rx = &dma_rx;
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struct pci_dev *dma_dev;
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dma_cap_mask_t mask;
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/*
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* Get pci device for DMA controller, currently it could only
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* be the DMA controller of Medfield
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*/
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dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
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if (!dma_dev)
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return -ENODEV;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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/* 1. Init rx channel */
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rx->dma_dev = &dma_dev->dev;
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dws->rxchan = dma_request_channel(mask, dw_spi_dma_chan_filter, rx);
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if (!dws->rxchan)
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goto err_exit;
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/* 2. Init tx channel */
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tx->dma_dev = &dma_dev->dev;
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dws->txchan = dma_request_channel(mask, dw_spi_dma_chan_filter, tx);
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if (!dws->txchan)
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goto free_rxchan;
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dws->master->dma_rx = dws->rxchan;
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dws->master->dma_tx = dws->txchan;
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init_completion(&dws->dma_completion);
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dw_spi_dma_maxburst_init(dws);
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return 0;
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free_rxchan:
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dma_release_channel(dws->rxchan);
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dws->rxchan = NULL;
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err_exit:
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return -EBUSY;
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}
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static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
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{
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dws->rxchan = dma_request_slave_channel(dev, "rx");
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if (!dws->rxchan)
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return -ENODEV;
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dws->txchan = dma_request_slave_channel(dev, "tx");
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if (!dws->txchan) {
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dma_release_channel(dws->rxchan);
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dws->rxchan = NULL;
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return -ENODEV;
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}
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dws->master->dma_rx = dws->rxchan;
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dws->master->dma_tx = dws->txchan;
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init_completion(&dws->dma_completion);
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dw_spi_dma_maxburst_init(dws);
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return 0;
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}
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static void dw_spi_dma_exit(struct dw_spi *dws)
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{
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if (dws->txchan) {
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dmaengine_terminate_sync(dws->txchan);
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dma_release_channel(dws->txchan);
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}
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if (dws->rxchan) {
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dmaengine_terminate_sync(dws->rxchan);
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dma_release_channel(dws->rxchan);
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}
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dw_writel(dws, DW_SPI_DMACR, 0);
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}
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static irqreturn_t dw_spi_dma_transfer_handler(struct dw_spi *dws)
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{
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u16 irq_status = dw_readl(dws, DW_SPI_ISR);
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if (!irq_status)
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return IRQ_NONE;
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dw_readl(dws, DW_SPI_ICR);
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spi_reset_chip(dws);
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dev_err(&dws->master->dev, "%s: FIFO overrun/underrun\n", __func__);
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dws->master->cur_msg->status = -EIO;
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complete(&dws->dma_completion);
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return IRQ_HANDLED;
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}
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static bool dw_spi_can_dma(struct spi_controller *master,
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struct spi_device *spi, struct spi_transfer *xfer)
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{
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struct dw_spi *dws = spi_controller_get_devdata(master);
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return xfer->len > dws->fifo_len;
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}
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static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
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{
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if (n_bytes == 1)
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return DMA_SLAVE_BUSWIDTH_1_BYTE;
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else if (n_bytes == 2)
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return DMA_SLAVE_BUSWIDTH_2_BYTES;
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return DMA_SLAVE_BUSWIDTH_UNDEFINED;
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}
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static int dw_spi_dma_wait(struct dw_spi *dws, struct spi_transfer *xfer)
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{
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unsigned long long ms;
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ms = xfer->len * MSEC_PER_SEC * BITS_PER_BYTE;
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do_div(ms, xfer->effective_speed_hz);
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ms += ms + 200;
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if (ms > UINT_MAX)
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ms = UINT_MAX;
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ms = wait_for_completion_timeout(&dws->dma_completion,
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msecs_to_jiffies(ms));
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if (ms == 0) {
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dev_err(&dws->master->cur_msg->spi->dev,
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"DMA transaction timed out\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static inline bool dw_spi_dma_tx_busy(struct dw_spi *dws)
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{
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return !(dw_readl(dws, DW_SPI_SR) & SR_TF_EMPT);
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}
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static int dw_spi_dma_wait_tx_done(struct dw_spi *dws,
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struct spi_transfer *xfer)
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{
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int retry = WAIT_RETRIES;
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struct spi_delay delay;
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u32 nents;
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nents = dw_readl(dws, DW_SPI_TXFLR);
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delay.unit = SPI_DELAY_UNIT_SCK;
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delay.value = nents * dws->n_bytes * BITS_PER_BYTE;
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while (dw_spi_dma_tx_busy(dws) && retry--)
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spi_delay_exec(&delay, xfer);
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if (retry < 0) {
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dev_err(&dws->master->dev, "Tx hanged up\n");
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return -EIO;
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}
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return 0;
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}
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/*
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* dws->dma_chan_busy is set before the dma transfer starts, callback for tx
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* channel will clear a corresponding bit.
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*/
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static void dw_spi_dma_tx_done(void *arg)
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{
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struct dw_spi *dws = arg;
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clear_bit(TX_BUSY, &dws->dma_chan_busy);
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if (test_bit(RX_BUSY, &dws->dma_chan_busy))
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return;
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dw_writel(dws, DW_SPI_DMACR, 0);
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complete(&dws->dma_completion);
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}
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static struct dma_async_tx_descriptor *
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dw_spi_dma_prepare_tx(struct dw_spi *dws, struct spi_transfer *xfer)
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{
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struct dma_slave_config txconf;
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struct dma_async_tx_descriptor *txdesc;
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if (!xfer->tx_buf)
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return NULL;
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memset(&txconf, 0, sizeof(txconf));
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txconf.direction = DMA_MEM_TO_DEV;
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txconf.dst_addr = dws->dma_addr;
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txconf.dst_maxburst = dws->txburst;
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txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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txconf.dst_addr_width = dw_spi_dma_convert_width(dws->n_bytes);
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txconf.device_fc = false;
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dmaengine_slave_config(dws->txchan, &txconf);
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txdesc = dmaengine_prep_slave_sg(dws->txchan,
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xfer->tx_sg.sgl,
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xfer->tx_sg.nents,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!txdesc)
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return NULL;
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txdesc->callback = dw_spi_dma_tx_done;
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txdesc->callback_param = dws;
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return txdesc;
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}
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static inline bool dw_spi_dma_rx_busy(struct dw_spi *dws)
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{
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return !!(dw_readl(dws, DW_SPI_SR) & SR_RF_NOT_EMPT);
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}
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static int dw_spi_dma_wait_rx_done(struct dw_spi *dws)
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{
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int retry = WAIT_RETRIES;
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struct spi_delay delay;
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unsigned long ns, us;
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u32 nents;
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/*
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* It's unlikely that DMA engine is still doing the data fetching, but
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* if it's let's give it some reasonable time. The timeout calculation
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* is based on the synchronous APB/SSI reference clock rate, on a
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* number of data entries left in the Rx FIFO, times a number of clock
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* periods normally needed for a single APB read/write transaction
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* without PREADY signal utilized (which is true for the DW APB SSI
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* controller).
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*/
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nents = dw_readl(dws, DW_SPI_RXFLR);
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ns = 4U * NSEC_PER_SEC / dws->max_freq * nents;
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if (ns <= NSEC_PER_USEC) {
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delay.unit = SPI_DELAY_UNIT_NSECS;
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delay.value = ns;
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} else {
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us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
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delay.unit = SPI_DELAY_UNIT_USECS;
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delay.value = clamp_val(us, 0, USHRT_MAX);
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}
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while (dw_spi_dma_rx_busy(dws) && retry--)
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spi_delay_exec(&delay, NULL);
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if (retry < 0) {
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dev_err(&dws->master->dev, "Rx hanged up\n");
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return -EIO;
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}
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return 0;
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}
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/*
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* dws->dma_chan_busy is set before the dma transfer starts, callback for rx
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* channel will clear a corresponding bit.
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*/
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static void dw_spi_dma_rx_done(void *arg)
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{
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struct dw_spi *dws = arg;
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clear_bit(RX_BUSY, &dws->dma_chan_busy);
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if (test_bit(TX_BUSY, &dws->dma_chan_busy))
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return;
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dw_writel(dws, DW_SPI_DMACR, 0);
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complete(&dws->dma_completion);
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}
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static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
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struct spi_transfer *xfer)
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{
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struct dma_slave_config rxconf;
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struct dma_async_tx_descriptor *rxdesc;
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if (!xfer->rx_buf)
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return NULL;
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memset(&rxconf, 0, sizeof(rxconf));
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rxconf.direction = DMA_DEV_TO_MEM;
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rxconf.src_addr = dws->dma_addr;
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rxconf.src_maxburst = dws->rxburst;
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rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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rxconf.src_addr_width = dw_spi_dma_convert_width(dws->n_bytes);
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rxconf.device_fc = false;
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dmaengine_slave_config(dws->rxchan, &rxconf);
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rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
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xfer->rx_sg.sgl,
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xfer->rx_sg.nents,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!rxdesc)
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return NULL;
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rxdesc->callback = dw_spi_dma_rx_done;
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rxdesc->callback_param = dws;
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return rxdesc;
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}
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static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
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{
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u16 imr = 0, dma_ctrl = 0;
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dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);
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dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - dws->txburst);
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if (xfer->tx_buf)
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dma_ctrl |= SPI_DMA_TDMAE;
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if (xfer->rx_buf)
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dma_ctrl |= SPI_DMA_RDMAE;
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dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
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/* Set the interrupt mask */
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if (xfer->tx_buf)
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imr |= SPI_INT_TXOI;
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if (xfer->rx_buf)
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imr |= SPI_INT_RXUI | SPI_INT_RXOI;
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spi_umask_intr(dws, imr);
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reinit_completion(&dws->dma_completion);
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dws->transfer_handler = dw_spi_dma_transfer_handler;
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return 0;
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}
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static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
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{
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struct dma_async_tx_descriptor *txdesc, *rxdesc;
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int ret;
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/* Prepare the TX dma transfer */
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txdesc = dw_spi_dma_prepare_tx(dws, xfer);
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/* Prepare the RX dma transfer */
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rxdesc = dw_spi_dma_prepare_rx(dws, xfer);
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/* rx must be started before tx due to spi instinct */
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if (rxdesc) {
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set_bit(RX_BUSY, &dws->dma_chan_busy);
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dmaengine_submit(rxdesc);
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dma_async_issue_pending(dws->rxchan);
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}
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if (txdesc) {
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set_bit(TX_BUSY, &dws->dma_chan_busy);
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dmaengine_submit(txdesc);
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dma_async_issue_pending(dws->txchan);
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}
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ret = dw_spi_dma_wait(dws, xfer);
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if (ret)
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return ret;
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if (txdesc && dws->master->cur_msg->status == -EINPROGRESS) {
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ret = dw_spi_dma_wait_tx_done(dws, xfer);
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if (ret)
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return ret;
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}
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if (rxdesc && dws->master->cur_msg->status == -EINPROGRESS)
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ret = dw_spi_dma_wait_rx_done(dws);
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return ret;
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}
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static void dw_spi_dma_stop(struct dw_spi *dws)
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{
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if (test_bit(TX_BUSY, &dws->dma_chan_busy)) {
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dmaengine_terminate_sync(dws->txchan);
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clear_bit(TX_BUSY, &dws->dma_chan_busy);
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}
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if (test_bit(RX_BUSY, &dws->dma_chan_busy)) {
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dmaengine_terminate_sync(dws->rxchan);
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clear_bit(RX_BUSY, &dws->dma_chan_busy);
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}
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dw_writel(dws, DW_SPI_DMACR, 0);
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}
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static const struct dw_spi_dma_ops dw_spi_dma_mfld_ops = {
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.dma_init = dw_spi_dma_init_mfld,
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.dma_exit = dw_spi_dma_exit,
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.dma_setup = dw_spi_dma_setup,
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.can_dma = dw_spi_can_dma,
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.dma_transfer = dw_spi_dma_transfer,
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.dma_stop = dw_spi_dma_stop,
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};
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void dw_spi_dma_setup_mfld(struct dw_spi *dws)
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{
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dws->dma_ops = &dw_spi_dma_mfld_ops;
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}
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EXPORT_SYMBOL_GPL(dw_spi_dma_setup_mfld);
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static const struct dw_spi_dma_ops dw_spi_dma_generic_ops = {
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.dma_init = dw_spi_dma_init_generic,
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.dma_exit = dw_spi_dma_exit,
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.dma_setup = dw_spi_dma_setup,
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.can_dma = dw_spi_can_dma,
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.dma_transfer = dw_spi_dma_transfer,
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.dma_stop = dw_spi_dma_stop,
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};
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void dw_spi_dma_setup_generic(struct dw_spi *dws)
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{
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dws->dma_ops = &dw_spi_dma_generic_ops;
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}
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EXPORT_SYMBOL_GPL(dw_spi_dma_setup_generic);
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