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8c83a607a5
Add the definitions of peripheral and system registers for sam9x5 chips family. Signed-off-by: Dan Liang <dan.liang@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
54 lines
2.4 KiB
C
54 lines
2.4 KiB
C
/*
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* Matrix-centric header file for the AT91SAM9x5 family
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*
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* Copyright (C) 2009-2012 Atmel Corporation.
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*
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* Only EBI related registers.
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* Write Protect register definitions may be useful.
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*
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* Licensed under GPLv2 or later.
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*/
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#ifndef AT91SAM9X5_MATRIX_H
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#define AT91SAM9X5_MATRIX_H
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#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
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#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
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#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
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#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
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#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
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#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
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#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
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#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
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#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
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#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
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#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
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#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
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#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
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#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
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#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
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#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
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#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
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#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
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#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
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#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
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#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
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#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
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#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
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#define AT91_MATRIX_MP_OFF (0 << 25)
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#define AT91_MATRIX_MP_ON (1 << 25)
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#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
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#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
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#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
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#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
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#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
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#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
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#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
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#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
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#define AT91_MATRIX_WPSR_WPV (1 << 0)
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#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
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#endif
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