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4f1d841475
While the addition of these properties is technically correct it unveils
a bug with deferred probe. The problem is that the presence of the gpio-
range property causes the gpio-tegra driver to defer probe (it needs the
pinctrl driver to be ready). That's technically correct, but it causes a
couple of issues:
- The keyboard on Chromebooks stops working. The reason for that is
that the gpio-tegra device has not registered an IRQ domain by the
time the EC SPI device is registered, hence the interrupt number
resolves to 0. This is technically a bug in the SPI core, since it
should really resolve the interrupt at probe time and defer if the
IRQ domain isn't available yet. This is similar to what's done for
I2C and platform device already.
- The gpio-tegra device deferring probe means that it is moved to the
end of the dpm_list. This list defines the suspend/resume order for
devices. However the core lacks a way to move all users of the
gpio-tegra device to the end of the dpm_list at the same time. This
in turn results in a subtle bug on Jetson TK1, where the gpio-keys
device is used to expose the power key as input. The power key is a
convenient way to wake the system from suspend. Interestingly, the
gpio-keys device ends up getting probed at a point after gpio-tegra
has been probed successfully from having been deferred earlier. As
such the driver doesn't need to defer the probe itself, and hence
the device isn't moved to the end of the dpm_list. This causes the
gpio-tegra device to be suspended before gpio-keys, which in turn
leaves gpio-keys unable to wake the system from suspend.
There are patches in the works to fix both of the above issues, but they
are too involved to make it into v4.3, so in the meantime let's fix the
regressions by commenting out the gpio-ranges properties until the fixes
have landed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
788 lines
21 KiB
Plaintext
788 lines
21 KiB
Plaintext
#include <dt-bindings/clock/tegra114-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/memory/tegra114-mc.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra114";
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interrupt-parent = <&lic>;
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host1x@50000000 {
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compatible = "nvidia,tegra114-host1x", "simple-bus";
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reg = <0x50000000 0x00028000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
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clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
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resets = <&tegra_car 28>;
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reset-names = "host1x";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x54000000 0x54000000 0x01000000>;
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gr2d@54140000 {
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compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
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reg = <0x54140000 0x00040000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_GR2D>;
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resets = <&tegra_car 21>;
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reset-names = "2d";
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};
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gr3d@54180000 {
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compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
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reg = <0x54180000 0x00040000>;
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clocks = <&tegra_car TEGRA114_CLK_GR3D>;
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resets = <&tegra_car 24>;
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reset-names = "3d";
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};
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dc@54200000 {
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compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
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reg = <0x54200000 0x00040000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_DISP1>,
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<&tegra_car TEGRA114_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 27>;
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reset-names = "dc";
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iommus = <&mc TEGRA_SWGROUP_DC>;
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nvidia,head = <0>;
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rgb {
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status = "disabled";
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};
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};
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dc@54240000 {
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compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
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reg = <0x54240000 0x00040000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_DISP2>,
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<&tegra_car TEGRA114_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 26>;
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reset-names = "dc";
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iommus = <&mc TEGRA_SWGROUP_DCB>;
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nvidia,head = <1>;
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rgb {
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status = "disabled";
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};
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};
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hdmi@54280000 {
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compatible = "nvidia,tegra114-hdmi";
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reg = <0x54280000 0x00040000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_HDMI>,
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<&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
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clock-names = "hdmi", "parent";
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resets = <&tegra_car 51>;
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reset-names = "hdmi";
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status = "disabled";
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};
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dsi@54300000 {
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compatible = "nvidia,tegra114-dsi";
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reg = <0x54300000 0x00040000>;
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clocks = <&tegra_car TEGRA114_CLK_DSIA>,
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<&tegra_car TEGRA114_CLK_DSIALP>,
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<&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
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clock-names = "dsi", "lp", "parent";
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resets = <&tegra_car 48>;
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reset-names = "dsi";
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nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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dsi@54400000 {
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compatible = "nvidia,tegra114-dsi";
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reg = <0x54400000 0x00040000>;
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clocks = <&tegra_car TEGRA114_CLK_DSIB>,
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<&tegra_car TEGRA114_CLK_DSIBLP>,
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<&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
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clock-names = "dsi", "lp", "parent";
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resets = <&tegra_car 82>;
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reset-names = "dsi";
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nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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gic: interrupt-controller@50041000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x50041000 0x1000>,
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<0x50042000 0x1000>,
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<0x50044000 0x2000>,
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<0x50046000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-parent = <&gic>;
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};
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lic: interrupt-controller@60004000 {
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compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
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reg = <0x60004000 0x100>,
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<0x60004100 0x50>,
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<0x60004200 0x50>,
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<0x60004300 0x50>,
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<0x60004400 0x50>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_TIMER>;
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};
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tegra_car: clock@60006000 {
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compatible = "nvidia,tegra114-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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flow-controller@60007000 {
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compatible = "nvidia,tegra114-flowctrl";
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reg = <0x60007000 0x1000>;
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};
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apbdma: dma@6000a000 {
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compatible = "nvidia,tegra114-apbdma";
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reg = <0x6000a000 0x1400>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
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resets = <&tegra_car 34>;
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reset-names = "dma";
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#dma-cells = <1>;
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};
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ahb: ahb@6000c000 {
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compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
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reg = <0x6000c000 0x150>;
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};
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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/*
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gpio-ranges = <&pinmux 0 0 246>;
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*/
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};
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apbmisc@70000800 {
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compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
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reg = <0x70000800 0x64 /* Chip revision */
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0x70000008 0x04>; /* Strapping options */
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};
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pinmux: pinmux@70000868 {
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compatible = "nvidia,tegra114-pinmux";
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reg = <0x70000868 0x148 /* Pad control registers */
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0x70003000 0x40c>; /* Mux registers */
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};
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/*
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* There are two serial driver i.e. 8250 based simple serial
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* driver and APB DMA based serial driver for higher baudrate
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* and performace. To enable the 8250 based driver, the compatible
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* is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
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* the APB DMA based serial driver, the comptible is
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* "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
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*/
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uarta: serial@70006000 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_UARTA>;
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resets = <&tegra_car 6>;
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reset-names = "serial";
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dmas = <&apbdma 8>, <&apbdma 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uartb: serial@70006040 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_UARTB>;
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resets = <&tegra_car 7>;
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reset-names = "serial";
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dmas = <&apbdma 9>, <&apbdma 9>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uartc: serial@70006200 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_UARTC>;
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resets = <&tegra_car 55>;
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reset-names = "serial";
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dmas = <&apbdma 10>, <&apbdma 10>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uartd: serial@70006300 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_UARTD>;
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resets = <&tegra_car 65>;
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reset-names = "serial";
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dmas = <&apbdma 19>, <&apbdma 19>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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pwm: pwm@7000a000 {
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compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
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reg = <0x7000a000 0x100>;
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#pwm-cells = <2>;
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clocks = <&tegra_car TEGRA114_CLK_PWM>;
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resets = <&tegra_car 17>;
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reset-names = "pwm";
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status = "disabled";
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};
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i2c@7000c000 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000c000 0x100>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_I2C1>;
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clock-names = "div-clk";
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resets = <&tegra_car 12>;
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reset-names = "i2c";
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dmas = <&apbdma 21>, <&apbdma 21>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@7000c400 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000c400 0x100>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_I2C2>;
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clock-names = "div-clk";
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resets = <&tegra_car 54>;
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reset-names = "i2c";
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dmas = <&apbdma 22>, <&apbdma 22>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@7000c500 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000c500 0x100>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_I2C3>;
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clock-names = "div-clk";
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resets = <&tegra_car 67>;
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reset-names = "i2c";
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dmas = <&apbdma 23>, <&apbdma 23>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@7000c700 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000c700 0x100>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_I2C4>;
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clock-names = "div-clk";
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resets = <&tegra_car 103>;
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reset-names = "i2c";
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dmas = <&apbdma 26>, <&apbdma 26>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@7000d000 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000d000 0x100>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_I2C5>;
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clock-names = "div-clk";
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resets = <&tegra_car 47>;
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reset-names = "i2c";
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dmas = <&apbdma 24>, <&apbdma 24>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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spi@7000d400 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000d400 0x200>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA114_CLK_SBC1>;
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clock-names = "spi";
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resets = <&tegra_car 41>;
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reset-names = "spi";
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dmas = <&apbdma 15>, <&apbdma 15>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d600 {
|
|
compatible = "nvidia,tegra114-spi";
|
|
reg = <0x7000d600 0x200>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA114_CLK_SBC2>;
|
|
clock-names = "spi";
|
|
resets = <&tegra_car 44>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 16>, <&apbdma 16>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d800 {
|
|
compatible = "nvidia,tegra114-spi";
|
|
reg = <0x7000d800 0x200>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA114_CLK_SBC3>;
|
|
clock-names = "spi";
|
|
resets = <&tegra_car 46>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 17>, <&apbdma 17>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000da00 {
|
|
compatible = "nvidia,tegra114-spi";
|
|
reg = <0x7000da00 0x200>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA114_CLK_SBC4>;
|
|
clock-names = "spi";
|
|
resets = <&tegra_car 68>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 18>, <&apbdma 18>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000dc00 {
|
|
compatible = "nvidia,tegra114-spi";
|
|
reg = <0x7000dc00 0x200>;
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA114_CLK_SBC5>;
|
|
clock-names = "spi";
|
|
resets = <&tegra_car 104>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 27>, <&apbdma 27>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000de00 {
|
|
compatible = "nvidia,tegra114-spi";
|
|
reg = <0x7000de00 0x200>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA114_CLK_SBC6>;
|
|
clock-names = "spi";
|
|
resets = <&tegra_car 105>;
|
|
reset-names = "spi";
|
|
dmas = <&apbdma 28>, <&apbdma 28>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc@7000e000 {
|
|
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
|
|
reg = <0x7000e000 0x100>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA114_CLK_RTC>;
|
|
};
|
|
|
|
kbc@7000e200 {
|
|
compatible = "nvidia,tegra114-kbc";
|
|
reg = <0x7000e200 0x100>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA114_CLK_KBC>;
|
|
resets = <&tegra_car 36>;
|
|
reset-names = "kbc";
|
|
status = "disabled";
|
|
};
|
|
|
|
pmc@7000e400 {
|
|
compatible = "nvidia,tegra114-pmc";
|
|
reg = <0x7000e400 0x400>;
|
|
clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
|
|
clock-names = "pclk", "clk32k_in";
|
|
};
|
|
|
|
fuse@7000f800 {
|
|
compatible = "nvidia,tegra114-efuse";
|
|
reg = <0x7000f800 0x400>;
|
|
clocks = <&tegra_car TEGRA114_CLK_FUSE>;
|
|
clock-names = "fuse";
|
|
resets = <&tegra_car 39>;
|
|
reset-names = "fuse";
|
|
};
|
|
|
|
mc: memory-controller@70019000 {
|
|
compatible = "nvidia,tegra114-mc";
|
|
reg = <0x70019000 0x1000>;
|
|
clocks = <&tegra_car TEGRA114_CLK_MC>;
|
|
clock-names = "mc";
|
|
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ahub@70080000 {
|
|
compatible = "nvidia,tegra114-ahub";
|
|
reg = <0x70080000 0x200>,
|
|
<0x70080200 0x100>,
|
|
<0x70081000 0x200>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
|
|
<&tegra_car TEGRA114_CLK_APBIF>;
|
|
clock-names = "d_audio", "apbif";
|
|
resets = <&tegra_car 106>, /* d_audio */
|
|
<&tegra_car 107>, /* apbif */
|
|
<&tegra_car 30>, /* i2s0 */
|
|
<&tegra_car 11>, /* i2s1 */
|
|
<&tegra_car 18>, /* i2s2 */
|
|
<&tegra_car 101>, /* i2s3 */
|
|
<&tegra_car 102>, /* i2s4 */
|
|
<&tegra_car 108>, /* dam0 */
|
|
<&tegra_car 109>, /* dam1 */
|
|
<&tegra_car 110>, /* dam2 */
|
|
<&tegra_car 10>, /* spdif */
|
|
<&tegra_car 153>, /* amx */
|
|
<&tegra_car 154>; /* adx */
|
|
reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
|
|
"i2s3", "i2s4", "dam0", "dam1", "dam2",
|
|
"spdif", "amx", "adx";
|
|
dmas = <&apbdma 1>, <&apbdma 1>,
|
|
<&apbdma 2>, <&apbdma 2>,
|
|
<&apbdma 3>, <&apbdma 3>,
|
|
<&apbdma 4>, <&apbdma 4>,
|
|
<&apbdma 6>, <&apbdma 6>,
|
|
<&apbdma 7>, <&apbdma 7>,
|
|
<&apbdma 12>, <&apbdma 12>,
|
|
<&apbdma 13>, <&apbdma 13>,
|
|
<&apbdma 14>, <&apbdma 14>,
|
|
<&apbdma 29>, <&apbdma 29>;
|
|
dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
|
|
"rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
|
|
"rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
|
|
"rx9", "tx9";
|
|
ranges;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
tegra_i2s0: i2s@70080300 {
|
|
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
|
|
reg = <0x70080300 0x100>;
|
|
nvidia,ahub-cif-ids = <4 4>;
|
|
clocks = <&tegra_car TEGRA114_CLK_I2S0>;
|
|
resets = <&tegra_car 30>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s1: i2s@70080400 {
|
|
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
|
|
reg = <0x70080400 0x100>;
|
|
nvidia,ahub-cif-ids = <5 5>;
|
|
clocks = <&tegra_car TEGRA114_CLK_I2S1>;
|
|
resets = <&tegra_car 11>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s2: i2s@70080500 {
|
|
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
|
|
reg = <0x70080500 0x100>;
|
|
nvidia,ahub-cif-ids = <6 6>;
|
|
clocks = <&tegra_car TEGRA114_CLK_I2S2>;
|
|
resets = <&tegra_car 18>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s3: i2s@70080600 {
|
|
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
|
|
reg = <0x70080600 0x100>;
|
|
nvidia,ahub-cif-ids = <7 7>;
|
|
clocks = <&tegra_car TEGRA114_CLK_I2S3>;
|
|
resets = <&tegra_car 101>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s4: i2s@70080700 {
|
|
compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
|
|
reg = <0x70080700 0x100>;
|
|
nvidia,ahub-cif-ids = <8 8>;
|
|
clocks = <&tegra_car TEGRA114_CLK_I2S4>;
|
|
resets = <&tegra_car 102>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
mipi: mipi@700e3000 {
|
|
compatible = "nvidia,tegra114-mipi";
|
|
reg = <0x700e3000 0x100>;
|
|
clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
|
|
#nvidia,mipi-calibrate-cells = <1>;
|
|
};
|
|
|
|
sdhci@78000000 {
|
|
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
|
|
reg = <0x78000000 0x200>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
|
|
resets = <&tegra_car 14>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@78000200 {
|
|
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
|
|
reg = <0x78000200 0x200>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
|
|
resets = <&tegra_car 9>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@78000400 {
|
|
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
|
|
reg = <0x78000400 0x200>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
|
|
resets = <&tegra_car 69>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@78000600 {
|
|
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
|
|
reg = <0x78000600 0x200>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
|
|
resets = <&tegra_car 15>;
|
|
reset-names = "sdhci";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@7d000000 {
|
|
compatible = "nvidia,tegra30-ehci", "usb-ehci";
|
|
reg = <0x7d000000 0x4000>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA114_CLK_USBD>;
|
|
resets = <&tegra_car 22>;
|
|
reset-names = "usb";
|
|
nvidia,phy = <&phy1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy1: usb-phy@7d000000 {
|
|
compatible = "nvidia,tegra30-usb-phy";
|
|
reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA114_CLK_USBD>,
|
|
<&tegra_car TEGRA114_CLK_PLL_U>,
|
|
<&tegra_car TEGRA114_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "utmi-pads";
|
|
resets = <&tegra_car 22>, <&tegra_car 22>;
|
|
reset-names = "usb", "utmi-pads";
|
|
nvidia,hssync-start-delay = <0>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <9>;
|
|
nvidia,xcvr-lsfslew = <0>;
|
|
nvidia,xcvr-lsrslew = <3>;
|
|
nvidia,hssquelch-level = <2>;
|
|
nvidia,hsdiscon-level = <5>;
|
|
nvidia,xcvr-hsslew = <12>;
|
|
nvidia,has-utmi-pad-registers;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@7d008000 {
|
|
compatible = "nvidia,tegra30-ehci", "usb-ehci";
|
|
reg = <0x7d008000 0x4000>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA114_CLK_USB3>;
|
|
resets = <&tegra_car 59>;
|
|
reset-names = "usb";
|
|
nvidia,phy = <&phy3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy3: usb-phy@7d008000 {
|
|
compatible = "nvidia,tegra30-usb-phy";
|
|
reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA114_CLK_USB3>,
|
|
<&tegra_car TEGRA114_CLK_PLL_U>,
|
|
<&tegra_car TEGRA114_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "utmi-pads";
|
|
resets = <&tegra_car 59>, <&tegra_car 22>;
|
|
reset-names = "usb", "utmi-pads";
|
|
nvidia,hssync-start-delay = <0>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <9>;
|
|
nvidia,xcvr-lsfslew = <0>;
|
|
nvidia,xcvr-lsrslew = <3>;
|
|
nvidia,hssquelch-level = <2>;
|
|
nvidia,hsdiscon-level = <5>;
|
|
nvidia,xcvr-hsslew = <12>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <1>;
|
|
};
|
|
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <2>;
|
|
};
|
|
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a15";
|
|
reg = <3>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupts =
|
|
<GIC_PPI 13
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
interrupt-parent = <&gic>;
|
|
};
|
|
};
|