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The DSS fclk and iclk handles are named differently on OMAP3430 ES1 than on later OMAP revisions. The ES1 has handles 'dss1_alwon_fck_3430es1' and 'dss_ick_3430es1', whereas later revisions have similar names but ending with 'es2'. This means we don't have one clock handle to which we could refer to when defining the DSS clocks. However, as the namespaces are separate for ES1 and ES2+ OMAPs, we can just rename the handles to 'dss1_alwon_fck' and 'dss_ick' for both ES1 and ES2+, removing the issue. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Tested-by: Christoph Fritz <chf.fritz@googlemail.com> Tested-by: Marek Belisko <marek@goldelico.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
209 lines
4.8 KiB
Plaintext
209 lines
4.8 KiB
Plaintext
/*
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* Device Tree Source for OMAP3430 ES1 clock data
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&cm_clocks {
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gfx_l3_ck: gfx_l3_ck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&l3_ick>;
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reg = <0x0b10>;
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ti,bit-shift = <0>;
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};
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gfx_l3_fck: gfx_l3_fck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&l3_ick>;
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ti,max-div = <7>;
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reg = <0x0b40>;
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ti,index-starts-at-one;
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};
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gfx_l3_ick: gfx_l3_ick {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&gfx_l3_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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gfx_cg1_ck: gfx_cg1_ck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&gfx_l3_fck>;
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reg = <0x0b00>;
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ti,bit-shift = <1>;
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};
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gfx_cg2_ck: gfx_cg2_ck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&gfx_l3_fck>;
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reg = <0x0b00>;
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ti,bit-shift = <2>;
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};
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d2d_26m_fck: d2d_26m_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&sys_ck>;
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reg = <0x0a00>;
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ti,bit-shift = <3>;
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};
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fshostusb_fck: fshostusb_fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&core_48m_fck>;
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reg = <0x0a00>;
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ti,bit-shift = <5>;
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};
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ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&corex2_fck>;
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ti,bit-shift = <0>;
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reg = <0x0a00>;
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};
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ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&corex2_fck>;
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ti,bit-shift = <8>;
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reg = <0x0a40>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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};
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ssi_ssr_fck: ssi_ssr_fck_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
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};
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ssi_sst_fck: ssi_sst_fck_3430es1 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&ssi_ssr_fck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,omap3-no-wait-interface-clock";
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clocks = <&core_l3_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <4>;
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};
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fac_ick: fac_ick {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&core_l4_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <8>;
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};
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ssi_l4_ick: ssi_l4_ick {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&l4_ick>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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ssi_ick: ssi_ick_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,omap3-no-wait-interface-clock";
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clocks = <&ssi_l4_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <0>;
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};
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usb_l4_gate_ick: usb_l4_gate_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-interface-clock";
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clocks = <&l4_ick>;
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ti,bit-shift = <5>;
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reg = <0x0a10>;
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};
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usb_l4_div_ick: usb_l4_div_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&l4_ick>;
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ti,bit-shift = <4>;
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ti,max-div = <1>;
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reg = <0x0a40>;
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ti,index-starts-at-one;
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};
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usb_l4_ick: usb_l4_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
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};
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dss1_alwon_fck: dss1_alwon_fck_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll4_m4x2_ck>;
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ti,bit-shift = <0>;
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reg = <0x0e00>;
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ti,set-rate-parent;
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};
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dss_ick: dss_ick_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,omap3-no-wait-interface-clock";
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clocks = <&l4_ick>;
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reg = <0x0e10>;
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ti,bit-shift = <0>;
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};
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};
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&cm_clockdomains {
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core_l3_clkdm: core_l3_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
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};
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gfx_3430es1_clkdm: gfx_3430es1_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
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};
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dss_clkdm: dss_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
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<&dss1_alwon_fck>, <&dss_ick>;
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};
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d2d_clkdm: d2d_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&d2d_26m_fck>;
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};
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core_l4_clkdm: core_l4_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
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<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
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<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
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<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
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<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
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<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
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<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
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<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
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<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
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<&fshostusb_fck>, <&fac_ick>, <&ssi_ick>;
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};
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};
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