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1a64634255
It'd be pretty awesome if someone would care enough to port this all properly to a class interface, perhaps submitting a command stream to the core via a sw object on PFIFO (emulating how EVO works basically, and also what nvidia have done forever..).. But, this seems unlikely given how old this hardware is now, so, lets just hide it away. There's a heap of other bits and pieces laying around that are still tangled. I'll (re)move them in pieces. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
354 lines
9.0 KiB
C
354 lines
9.0 KiB
C
/*
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* Copyright 2011 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <drm/drmP.h>
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#include "nouveau_drm.h"
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#include "nouveau_bios.h"
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#include "nouveau_pm.h"
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#include "dispnv04/hw.h"
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#include <subdev/bios/pll.h>
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#include <subdev/clock.h>
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#include <subdev/timer.h>
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#include <engine/fifo.h>
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#define min2(a,b) ((a) < (b) ? (a) : (b))
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static u32
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read_pll_1(struct drm_device *dev, u32 reg)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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u32 ctrl = nv_rd32(device, reg + 0x00);
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int P = (ctrl & 0x00070000) >> 16;
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int N = (ctrl & 0x0000ff00) >> 8;
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int M = (ctrl & 0x000000ff) >> 0;
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u32 ref = 27000, clk = 0;
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if (ctrl & 0x80000000)
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clk = ref * N / M;
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return clk >> P;
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}
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static u32
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read_pll_2(struct drm_device *dev, u32 reg)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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u32 ctrl = nv_rd32(device, reg + 0x00);
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u32 coef = nv_rd32(device, reg + 0x04);
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int N2 = (coef & 0xff000000) >> 24;
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int M2 = (coef & 0x00ff0000) >> 16;
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int N1 = (coef & 0x0000ff00) >> 8;
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int M1 = (coef & 0x000000ff) >> 0;
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int P = (ctrl & 0x00070000) >> 16;
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u32 ref = 27000, clk = 0;
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if ((ctrl & 0x80000000) && M1) {
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clk = ref * N1 / M1;
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if ((ctrl & 0x40000100) == 0x40000000) {
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if (M2)
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clk = clk * N2 / M2;
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else
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clk = 0;
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}
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}
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return clk >> P;
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}
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static u32
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read_clk(struct drm_device *dev, u32 src)
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{
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switch (src) {
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case 3:
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return read_pll_2(dev, 0x004000);
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case 2:
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return read_pll_1(dev, 0x004008);
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default:
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break;
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}
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return 0;
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}
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int
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nv40_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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u32 ctrl = nv_rd32(device, 0x00c040);
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perflvl->core = read_clk(dev, (ctrl & 0x00000003) >> 0);
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perflvl->shader = read_clk(dev, (ctrl & 0x00000030) >> 4);
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perflvl->memory = read_pll_2(dev, 0x4020);
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return 0;
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}
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struct nv40_pm_state {
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u32 ctrl;
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u32 npll_ctrl;
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u32 npll_coef;
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u32 spll;
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u32 mpll_ctrl;
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u32 mpll_coef;
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};
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static int
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nv40_calc_pll(struct drm_device *dev, u32 reg, struct nvbios_pll *pll,
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u32 clk, int *N1, int *M1, int *N2, int *M2, int *log2P)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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struct nouveau_bios *bios = nouveau_bios(device);
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struct nouveau_clock *pclk = nouveau_clock(device);
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struct nouveau_pll_vals coef;
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int ret;
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ret = nvbios_pll_parse(bios, reg, pll);
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if (ret)
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return ret;
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if (clk < pll->vco1.max_freq)
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pll->vco2.max_freq = 0;
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pclk->pll_calc(pclk, pll, clk, &coef);
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if (ret == 0)
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return -ERANGE;
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*N1 = coef.N1;
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*M1 = coef.M1;
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if (N2 && M2) {
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if (pll->vco2.max_freq) {
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*N2 = coef.N2;
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*M2 = coef.M2;
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} else {
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*N2 = 1;
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*M2 = 1;
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}
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}
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*log2P = coef.log2P;
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return 0;
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}
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void *
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nv40_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
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{
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struct nv40_pm_state *info;
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struct nvbios_pll pll;
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int N1, N2, M1, M2, log2P;
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int ret;
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info = kmalloc(sizeof(*info), GFP_KERNEL);
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if (!info)
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return ERR_PTR(-ENOMEM);
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/* core/geometric clock */
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ret = nv40_calc_pll(dev, 0x004000, &pll, perflvl->core,
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&N1, &M1, &N2, &M2, &log2P);
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if (ret < 0)
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goto out;
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if (N2 == M2) {
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info->npll_ctrl = 0x80000100 | (log2P << 16);
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info->npll_coef = (N1 << 8) | M1;
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} else {
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info->npll_ctrl = 0xc0000000 | (log2P << 16);
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info->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
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}
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/* use the second PLL for shader/rop clock, if it differs from core */
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if (perflvl->shader && perflvl->shader != perflvl->core) {
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ret = nv40_calc_pll(dev, 0x004008, &pll, perflvl->shader,
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&N1, &M1, NULL, NULL, &log2P);
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if (ret < 0)
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goto out;
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info->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
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info->ctrl = 0x00000223;
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} else {
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info->spll = 0x00000000;
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info->ctrl = 0x00000333;
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}
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/* memory clock */
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if (!perflvl->memory) {
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info->mpll_ctrl = 0x00000000;
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goto out;
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}
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ret = nv40_calc_pll(dev, 0x004020, &pll, perflvl->memory,
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&N1, &M1, &N2, &M2, &log2P);
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if (ret < 0)
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goto out;
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info->mpll_ctrl = 0x80000000 | (log2P << 16);
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info->mpll_ctrl |= min2(pll.bias_p + log2P, pll.max_p) << 20;
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if (N2 == M2) {
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info->mpll_ctrl |= 0x00000100;
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info->mpll_coef = (N1 << 8) | M1;
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} else {
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info->mpll_ctrl |= 0x40000000;
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info->mpll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
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}
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out:
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if (ret < 0) {
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kfree(info);
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info = ERR_PTR(ret);
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}
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return info;
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}
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static bool
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nv40_pm_gr_idle(void *data)
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{
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struct drm_device *dev = data;
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struct nouveau_device *device = nouveau_dev(dev);
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if ((nv_rd32(device, 0x400760) & 0x000000f0) >> 4 !=
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(nv_rd32(device, 0x400760) & 0x0000000f))
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return false;
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if (nv_rd32(device, 0x400700))
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return false;
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return true;
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}
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int
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nv40_pm_clocks_set(struct drm_device *dev, void *pre_state)
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{
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struct nouveau_device *device = nouveau_dev(dev);
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struct nouveau_fifo *pfifo = nouveau_fifo(device);
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nv40_pm_state *info = pre_state;
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unsigned long flags;
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struct bit_entry M;
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u32 crtc_mask = 0;
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u8 sr1[2];
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int i, ret = -EAGAIN;
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/* determine which CRTCs are active, fetch VGA_SR1 for each */
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for (i = 0; i < 2; i++) {
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u32 vbl = nv_rd32(device, 0x600808 + (i * 0x2000));
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u32 cnt = 0;
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do {
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if (vbl != nv_rd32(device, 0x600808 + (i * 0x2000))) {
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nv_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
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sr1[i] = nv_rd08(device, 0x0c03c5 + (i * 0x2000));
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if (!(sr1[i] & 0x20))
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crtc_mask |= (1 << i);
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break;
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}
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udelay(1);
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} while (cnt++ < 32);
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}
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/* halt and idle engines */
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pfifo->pause(pfifo, &flags);
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if (!nv_wait_cb(device, nv40_pm_gr_idle, dev))
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goto resume;
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ret = 0;
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/* set engine clocks */
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nv_mask(device, 0x00c040, 0x00000333, 0x00000000);
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nv_wr32(device, 0x004004, info->npll_coef);
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nv_mask(device, 0x004000, 0xc0070100, info->npll_ctrl);
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nv_mask(device, 0x004008, 0xc007ffff, info->spll);
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mdelay(5);
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nv_mask(device, 0x00c040, 0x00000333, info->ctrl);
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if (!info->mpll_ctrl)
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goto resume;
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/* wait for vblank start on active crtcs, disable memory access */
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for (i = 0; i < 2; i++) {
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if (!(crtc_mask & (1 << i)))
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continue;
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nv_wait(device, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);
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nv_wait(device, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
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nv_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
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nv_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
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}
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/* prepare ram for reclocking */
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nv_wr32(device, 0x1002d4, 0x00000001); /* precharge */
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nv_wr32(device, 0x1002d0, 0x00000001); /* refresh */
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nv_wr32(device, 0x1002d0, 0x00000001); /* refresh */
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nv_mask(device, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
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nv_wr32(device, 0x1002dc, 0x00000001); /* enable self-refresh */
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/* change the PLL of each memory partition */
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nv_mask(device, 0x00c040, 0x0000c000, 0x00000000);
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switch (nv_device(drm->device)->chipset) {
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case 0x40:
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case 0x45:
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case 0x41:
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case 0x42:
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case 0x47:
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nv_mask(device, 0x004044, 0xc0771100, info->mpll_ctrl);
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nv_mask(device, 0x00402c, 0xc0771100, info->mpll_ctrl);
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nv_wr32(device, 0x004048, info->mpll_coef);
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nv_wr32(device, 0x004030, info->mpll_coef);
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case 0x43:
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case 0x49:
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case 0x4b:
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nv_mask(device, 0x004038, 0xc0771100, info->mpll_ctrl);
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nv_wr32(device, 0x00403c, info->mpll_coef);
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default:
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nv_mask(device, 0x004020, 0xc0771100, info->mpll_ctrl);
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nv_wr32(device, 0x004024, info->mpll_coef);
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break;
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}
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udelay(100);
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nv_mask(device, 0x00c040, 0x0000c000, 0x0000c000);
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/* re-enable normal operation of memory controller */
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nv_wr32(device, 0x1002dc, 0x00000000);
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nv_mask(device, 0x100210, 0x80000000, 0x80000000);
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udelay(100);
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/* execute memory reset script from vbios */
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if (!bit_table(dev, 'M', &M))
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nouveau_bios_run_init_table(dev, ROM16(M.data[0]), NULL, 0);
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/* make sure we're in vblank (hopefully the same one as before), and
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* then re-enable crtc memory access
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*/
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for (i = 0; i < 2; i++) {
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if (!(crtc_mask & (1 << i)))
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continue;
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nv_wait(device, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
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nv_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
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nv_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i]);
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}
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/* resume engines */
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resume:
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pfifo->start(pfifo, &flags);
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kfree(info);
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return ret;
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}
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