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Some Tegra20 boards don't have RAM code stored in NVMEM, which is used for the memory chip identification and the identity information should be read out from LPDDR2 chip in this case. Document new sub-node containing generic LPDDR2 properties that will be used for the memory chip identification if RAM code isn't available. The identification is done by reading out memory configuration values from generic LPDDR2 mode registers of SDRAM chip and comparing them with the values of device-tree 'lpddr2' sub-node. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211006224659.21434-8-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
250 lines
6.8 KiB
YAML
250 lines
6.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra20 SoC External Memory Controller
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maintainers:
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- Dmitry Osipenko <digetx@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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- Thierry Reding <thierry.reding@gmail.com>
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description: |
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The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
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service the request stream sent from Memory Controller. The EMC also has
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various performance-affecting settings beyond the obvious SDRAM configuration
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parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
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standard protocols: DDR1, LPDDR2 and DDR2.
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properties:
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compatible:
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const: nvidia,tegra20-emc
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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interrupts:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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"#interconnect-cells":
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const: 0
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nvidia,memory-controller:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle of the Memory Controller node.
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power-domains:
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maxItems: 1
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description:
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Phandle of the SoC "core" power domain.
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operating-points-v2:
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description:
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Should contain freqs and voltages and opp-supported-hw property, which
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is a bitfield indicating SoC process ID mask.
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nvidia,use-ram-code:
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type: boolean
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description:
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If present, the emc-tables@ sub-nodes will be addressed.
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$defs:
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emc-table:
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type: object
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properties:
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compatible:
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const: nvidia,tegra20-emc-table
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clock-frequency:
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description:
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Memory clock rate in kHz.
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minimum: 1000
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maximum: 900000
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reg:
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maxItems: 1
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description:
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Either an opaque enumerator to tell different tables apart, or
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the valid frequency for which the table should be used (in kHz).
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nvidia,emc-registers:
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description:
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EMC timing characterization data. These are the registers
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(see section "15.4.1 EMC Registers" in the TRM) whose values
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need to be specified, according to the board documentation.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: EMC_RC
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- description: EMC_RFC
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- description: EMC_RAS
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- description: EMC_RP
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- description: EMC_R2W
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- description: EMC_W2R
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- description: EMC_R2P
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- description: EMC_W2P
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- description: EMC_RD_RCD
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- description: EMC_WR_RCD
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- description: EMC_RRD
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- description: EMC_REXT
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- description: EMC_WDV
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- description: EMC_QUSE
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- description: EMC_QRST
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- description: EMC_QSAFE
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- description: EMC_RDV
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- description: EMC_REFRESH
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- description: EMC_BURST_REFRESH_NUM
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- description: EMC_PDEX2WR
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- description: EMC_PDEX2RD
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- description: EMC_PCHG2PDEN
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- description: EMC_ACT2PDEN
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- description: EMC_AR2PDEN
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- description: EMC_RW2PDEN
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- description: EMC_TXSR
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- description: EMC_TCKE
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- description: EMC_TFAW
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- description: EMC_TRPAB
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- description: EMC_TCLKSTABLE
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- description: EMC_TCLKSTOP
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- description: EMC_TREFBW
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- description: EMC_QUSE_EXTRA
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- description: EMC_FBIO_CFG6
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- description: EMC_ODT_WRITE
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- description: EMC_ODT_READ
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- description: EMC_FBIO_CFG5
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- description: EMC_CFG_DIG_DLL
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- description: EMC_DLL_XFORM_DQS
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- description: EMC_DLL_XFORM_QUSE
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- description: EMC_ZCAL_REF_CNT
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- description: EMC_ZCAL_WAIT_CNT
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- description: EMC_AUTO_CAL_INTERVAL
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- description: EMC_CFG_CLKTRIM_0
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- description: EMC_CFG_CLKTRIM_1
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- description: EMC_CFG_CLKTRIM_2
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required:
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- clock-frequency
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- compatible
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- reg
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- nvidia,emc-registers
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additionalProperties: false
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patternProperties:
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"^emc-table@[0-9]+$":
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$ref: "#/$defs/emc-table"
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"^emc-tables@[a-z0-9-]+$":
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type: object
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properties:
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reg:
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maxItems: 1
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description:
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An opaque enumerator to tell different tables apart.
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nvidia,ram-code:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Value of RAM_CODE this timing set is used for.
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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lpddr2:
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$ref: "ddr/jedec,lpddr2.yaml#"
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type: object
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patternProperties:
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"^emc-table@[0-9]+$":
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$ref: "#/$defs/emc-table"
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oneOf:
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- required:
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- nvidia,ram-code
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- required:
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- lpddr2
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- nvidia,memory-controller
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- "#interconnect-cells"
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- operating-points-v2
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additionalProperties: false
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examples:
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- |
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external-memory-controller@7000f400 {
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compatible = "nvidia,tegra20-emc";
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reg = <0x7000f400 0x400>;
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interrupts = <0 78 4>;
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clocks = <&clock_controller 57>;
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nvidia,memory-controller = <&mc>;
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operating-points-v2 = <&dvfs_opp_table>;
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power-domains = <&domain>;
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#interconnect-cells = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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nvidia,use-ram-code;
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emc-tables@0 {
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nvidia,ram-code = <0>;
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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emc-table@333000 {
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reg = <333000>;
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compatible = "nvidia,tegra20-emc-table";
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clock-frequency = <333000>;
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nvidia,emc-registers = <0x00000018 0x00000033
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0x00000012 0x00000004 0x00000004 0x00000005
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0x00000003 0x0000000c 0x00000006 0x00000006
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0x00000003 0x00000001 0x00000004 0x00000005
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0x00000004 0x00000009 0x0000000d 0x00000bff
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0x00000000 0x00000003 0x00000003 0x00000006
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0x00000006 0x00000001 0x00000011 0x000000c8
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0x00000003 0x0000000e 0x00000007 0x00000008
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0x00000002 0x00000000 0x00000000 0x00000002
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0x00000000 0x00000000 0x00000083 0xf0440303
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0x007fe010 0x00001414 0x00000000 0x00000000
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0x00000000 0x00000000 0x00000000 0x00000000>;
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};
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};
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emc-tables@1 {
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reg = <1>;
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lpddr2 {
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compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";
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revision-id1 = <1>;
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density = <2048>;
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io-width = <16>;
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};
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};
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};
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