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Change the EDAC internal representation to work with non-csrow based memory controllers. There are lots of those memory controllers nowadays, and more are coming. So, the EDAC internal representation needs to be changed, in order to work with those memory controllers, while preserving backward compatibility with the old ones. The edac core was written with the idea that memory controllers are able to directly access csrows. This is not true for FB-DIMM and RAMBUS memory controllers. Also, some recent advanced memory controllers don't present a per-csrows view. Instead, they view memories as DIMMs, instead of ranks. So, change the allocation and error report routines to allow them to work with all types of architectures. This will allow the removal of several hacks with FB-DIMM and RAMBUS memory controllers. Also, several tests were done on different platforms using different x86 drivers. TODO: a multi-rank DIMMs are currently represented by multiple DIMM entries in struct dimm_info. That means that changing a label for one rank won't change the same label for the other ranks at the same DIMM. This bug is present since the beginning of the EDAC, so it is not a big deal. However, on several drivers, it is possible to fix this issue, but it should be a per-driver fix, as the csrow => DIMM arrangement may not be equal for all. So, don't try to fix it here yet. I tried to make this patch as short as possible, preceding it with several other patches that simplified the logic here. Yet, as the internal API changes, all drivers need changes. The changes are generally bigger in the drivers for FB-DIMMs. Cc: Aristeu Rozanski <arozansk@redhat.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Cc: Mark Gross <mark.gross@intel.com> Cc: Jason Uhlenkott <juhlenko@akamai.com> Cc: Tim Small <tim@buttersideup.com> Cc: Ranganathan Desikan <ravi@jetztechnologies.com> Cc: "Arvind R." <arvino55@gmail.com> Cc: Olof Johansson <olof@lixom.net> Cc: Egor Martovetsky <egor@pasemi.com> Cc: Chris Metcalf <cmetcalf@tilera.com> Cc: Michal Marek <mmarek@suse.cz> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Joe Perches <joe@perches.com> Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Hitoshi Mitake <h.mitake@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
588 lines
17 KiB
C
588 lines
17 KiB
C
/*
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* Defines, structures, APIs for edac_core module
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*
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* (C) 2007 Linux Networx (http://lnxi.com)
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* This file may be distributed under the terms of the
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* GNU General Public License.
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*
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* Written by Thayne Harbaugh
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* Based on work by Dan Hollis <goemon at anime dot net> and others.
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* http://www.anime.net/~goemon/linux-ecc/
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*
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* NMI handling support added by
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* Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
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*
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* Refactored for multi-source files:
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* Doug Thompson <norsk5@xmission.com>
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*
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*/
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#ifndef _EDAC_CORE_H_
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#define _EDAC_CORE_H_
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/smp.h>
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#include <linux/pci.h>
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#include <linux/time.h>
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#include <linux/nmi.h>
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#include <linux/rcupdate.h>
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#include <linux/completion.h>
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#include <linux/kobject.h>
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#include <linux/platform_device.h>
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#include <linux/workqueue.h>
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#include <linux/edac.h>
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#define EDAC_DEVICE_NAME_LEN 31
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#define EDAC_ATTRIB_VALUE_LEN 15
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#if PAGE_SHIFT < 20
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#define PAGES_TO_MiB(pages) ((pages) >> (20 - PAGE_SHIFT))
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#define MiB_TO_PAGES(mb) ((mb) << (20 - PAGE_SHIFT))
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#else /* PAGE_SHIFT > 20 */
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#define PAGES_TO_MiB(pages) ((pages) << (PAGE_SHIFT - 20))
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#define MiB_TO_PAGES(mb) ((mb) >> (PAGE_SHIFT - 20))
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#endif
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#define edac_printk(level, prefix, fmt, arg...) \
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printk(level "EDAC " prefix ": " fmt, ##arg)
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#define edac_mc_printk(mci, level, fmt, arg...) \
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printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
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#define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
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printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
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#define edac_device_printk(ctl, level, fmt, arg...) \
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printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
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#define edac_pci_printk(ctl, level, fmt, arg...) \
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printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
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/* prefixes for edac_printk() and edac_mc_printk() */
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#define EDAC_MC "MC"
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#define EDAC_PCI "PCI"
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#define EDAC_DEBUG "DEBUG"
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extern const char *edac_mem_types[];
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#ifdef CONFIG_EDAC_DEBUG
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extern int edac_debug_level;
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#define edac_debug_printk(level, fmt, arg...) \
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do { \
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if (level <= edac_debug_level) \
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edac_printk(KERN_DEBUG, EDAC_DEBUG, \
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"%s: " fmt, __func__, ##arg); \
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} while (0)
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#define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
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#define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
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#define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
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#define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
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#define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
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#else /* !CONFIG_EDAC_DEBUG */
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#define debugf0( ... )
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#define debugf1( ... )
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#define debugf2( ... )
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#define debugf3( ... )
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#define debugf4( ... )
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#endif /* !CONFIG_EDAC_DEBUG */
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#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
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PCI_DEVICE_ID_ ## vend ## _ ## dev
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#define edac_dev_name(dev) (dev)->dev_name
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/*
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* The following are the structures to provide for a generic
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* or abstract 'edac_device'. This set of structures and the
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* code that implements the APIs for the same, provide for
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* registering EDAC type devices which are NOT standard memory.
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*
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* CPU caches (L1 and L2)
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* DMA engines
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* Core CPU swithces
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* Fabric switch units
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* PCIe interface controllers
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* other EDAC/ECC type devices that can be monitored for
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* errors, etc.
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*
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* It allows for a 2 level set of hiearchry. For example:
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*
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* cache could be composed of L1, L2 and L3 levels of cache.
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* Each CPU core would have its own L1 cache, while sharing
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* L2 and maybe L3 caches.
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*
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* View them arranged, via the sysfs presentation:
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* /sys/devices/system/edac/..
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*
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* mc/ <existing memory device directory>
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* cpu/cpu0/.. <L1 and L2 block directory>
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* /L1-cache/ce_count
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* /ue_count
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* /L2-cache/ce_count
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* /ue_count
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* cpu/cpu1/.. <L1 and L2 block directory>
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* /L1-cache/ce_count
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* /ue_count
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* /L2-cache/ce_count
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* /ue_count
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* ...
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*
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* the L1 and L2 directories would be "edac_device_block's"
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*/
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struct edac_device_counter {
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u32 ue_count;
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u32 ce_count;
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};
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/* forward reference */
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struct edac_device_ctl_info;
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struct edac_device_block;
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/* edac_dev_sysfs_attribute structure
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* used for driver sysfs attributes in mem_ctl_info
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* for extra controls and attributes:
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* like high level error Injection controls
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*/
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struct edac_dev_sysfs_attribute {
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struct attribute attr;
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ssize_t (*show)(struct edac_device_ctl_info *, char *);
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ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
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};
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/* edac_dev_sysfs_block_attribute structure
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*
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* used in leaf 'block' nodes for adding controls/attributes
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*
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* each block in each instance of the containing control structure
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* can have an array of the following. The show and store functions
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* will be filled in with the show/store function in the
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* low level driver.
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*
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* The 'value' field will be the actual value field used for
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* counting
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*/
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struct edac_dev_sysfs_block_attribute {
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struct attribute attr;
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ssize_t (*show)(struct kobject *, struct attribute *, char *);
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ssize_t (*store)(struct kobject *, struct attribute *,
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const char *, size_t);
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struct edac_device_block *block;
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unsigned int value;
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};
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/* device block control structure */
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struct edac_device_block {
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struct edac_device_instance *instance; /* Up Pointer */
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char name[EDAC_DEVICE_NAME_LEN + 1];
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struct edac_device_counter counters; /* basic UE and CE counters */
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int nr_attribs; /* how many attributes */
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/* this block's attributes, could be NULL */
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struct edac_dev_sysfs_block_attribute *block_attributes;
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/* edac sysfs device control */
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struct kobject kobj;
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};
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/* device instance control structure */
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struct edac_device_instance {
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struct edac_device_ctl_info *ctl; /* Up pointer */
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char name[EDAC_DEVICE_NAME_LEN + 4];
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struct edac_device_counter counters; /* instance counters */
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u32 nr_blocks; /* how many blocks */
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struct edac_device_block *blocks; /* block array */
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/* edac sysfs device control */
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struct kobject kobj;
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};
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/*
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* Abstract edac_device control info structure
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*
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*/
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struct edac_device_ctl_info {
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/* for global list of edac_device_ctl_info structs */
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struct list_head link;
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struct module *owner; /* Module owner of this control struct */
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int dev_idx;
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/* Per instance controls for this edac_device */
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int log_ue; /* boolean for logging UEs */
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int log_ce; /* boolean for logging CEs */
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int panic_on_ue; /* boolean for panic'ing on an UE */
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unsigned poll_msec; /* number of milliseconds to poll interval */
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unsigned long delay; /* number of jiffies for poll_msec */
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/* Additional top controller level attributes, but specified
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* by the low level driver.
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*
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* Set by the low level driver to provide attributes at the
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* controller level, same level as 'ue_count' and 'ce_count' above.
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* An array of structures, NULL terminated
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*
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* If attributes are desired, then set to array of attributes
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* If no attributes are desired, leave NULL
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*/
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struct edac_dev_sysfs_attribute *sysfs_attributes;
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/* pointer to main 'edac' subsys in sysfs */
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struct bus_type *edac_subsys;
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/* the internal state of this controller instance */
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int op_state;
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/* work struct for this instance */
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struct delayed_work work;
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/* pointer to edac polling checking routine:
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* If NOT NULL: points to polling check routine
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* If NULL: Then assumes INTERRUPT operation, where
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* MC driver will receive events
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*/
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void (*edac_check) (struct edac_device_ctl_info * edac_dev);
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struct device *dev; /* pointer to device structure */
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const char *mod_name; /* module name */
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const char *ctl_name; /* edac controller name */
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const char *dev_name; /* pci/platform/etc... name */
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void *pvt_info; /* pointer to 'private driver' info */
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unsigned long start_time; /* edac_device load start time (jiffies) */
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struct completion removal_complete;
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/* sysfs top name under 'edac' directory
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* and instance name:
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* cpu/cpu0/...
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* cpu/cpu1/...
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* cpu/cpu2/...
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* ...
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*/
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char name[EDAC_DEVICE_NAME_LEN + 1];
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/* Number of instances supported on this control structure
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* and the array of those instances
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*/
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u32 nr_instances;
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struct edac_device_instance *instances;
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/* Event counters for the this whole EDAC Device */
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struct edac_device_counter counters;
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/* edac sysfs device control for the 'name'
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* device this structure controls
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*/
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struct kobject kobj;
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};
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/* To get from the instance's wq to the beginning of the ctl structure */
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#define to_edac_mem_ctl_work(w) \
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container_of(w, struct mem_ctl_info, work)
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#define to_edac_device_ctl_work(w) \
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container_of(w,struct edac_device_ctl_info,work)
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/*
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* The alloc() and free() functions for the 'edac_device' control info
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* structure. A MC driver will allocate one of these for each edac_device
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* it is going to control/register with the EDAC CORE.
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*/
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extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
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unsigned sizeof_private,
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char *edac_device_name, unsigned nr_instances,
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char *edac_block_name, unsigned nr_blocks,
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unsigned offset_value,
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struct edac_dev_sysfs_block_attribute *block_attributes,
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unsigned nr_attribs,
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int device_index);
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/* The offset value can be:
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* -1 indicating no offset value
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* 0 for zero-based block numbers
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* 1 for 1-based block number
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* other for other-based block number
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*/
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#define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1)
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extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
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#ifdef CONFIG_PCI
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struct edac_pci_counter {
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atomic_t pe_count;
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atomic_t npe_count;
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};
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/*
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* Abstract edac_pci control info structure
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*
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*/
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struct edac_pci_ctl_info {
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/* for global list of edac_pci_ctl_info structs */
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struct list_head link;
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int pci_idx;
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struct bus_type *edac_subsys; /* pointer to subsystem */
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/* the internal state of this controller instance */
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int op_state;
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/* work struct for this instance */
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struct delayed_work work;
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/* pointer to edac polling checking routine:
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* If NOT NULL: points to polling check routine
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* If NULL: Then assumes INTERRUPT operation, where
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* MC driver will receive events
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*/
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void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
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struct device *dev; /* pointer to device structure */
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const char *mod_name; /* module name */
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const char *ctl_name; /* edac controller name */
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const char *dev_name; /* pci/platform/etc... name */
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void *pvt_info; /* pointer to 'private driver' info */
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unsigned long start_time; /* edac_pci load start time (jiffies) */
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struct completion complete;
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/* sysfs top name under 'edac' directory
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* and instance name:
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* cpu/cpu0/...
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* cpu/cpu1/...
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* cpu/cpu2/...
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* ...
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*/
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char name[EDAC_DEVICE_NAME_LEN + 1];
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/* Event counters for the this whole EDAC Device */
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struct edac_pci_counter counters;
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/* edac sysfs device control for the 'name'
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* device this structure controls
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*/
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struct kobject kobj;
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struct completion kobj_complete;
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};
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#define to_edac_pci_ctl_work(w) \
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container_of(w, struct edac_pci_ctl_info,work)
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/* write all or some bits in a byte-register*/
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static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
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u8 mask)
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{
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if (mask != 0xff) {
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u8 buf;
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pci_read_config_byte(pdev, offset, &buf);
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value &= mask;
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buf &= ~mask;
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value |= buf;
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}
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pci_write_config_byte(pdev, offset, value);
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}
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/* write all or some bits in a word-register*/
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static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
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u16 value, u16 mask)
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{
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if (mask != 0xffff) {
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u16 buf;
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pci_read_config_word(pdev, offset, &buf);
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value &= mask;
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buf &= ~mask;
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value |= buf;
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}
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pci_write_config_word(pdev, offset, value);
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}
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/*
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* pci_write_bits32
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*
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* edac local routine to do pci_write_config_dword, but adds
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* a mask parameter. If mask is all ones, ignore the mask.
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* Otherwise utilize the mask to isolate specified bits
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*
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* write all or some bits in a dword-register
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*/
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static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
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u32 value, u32 mask)
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{
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if (mask != 0xffffffff) {
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u32 buf;
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pci_read_config_dword(pdev, offset, &buf);
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value &= mask;
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buf &= ~mask;
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value |= buf;
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}
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pci_write_config_dword(pdev, offset, value);
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}
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#endif /* CONFIG_PCI */
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struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
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unsigned nr_chans, int edac_index);
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struct mem_ctl_info *new_edac_mc_alloc(unsigned edac_index,
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unsigned n_layers,
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struct edac_mc_layer *layers,
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unsigned sz_pvt);
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extern int edac_mc_add_mc(struct mem_ctl_info *mci);
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extern void edac_mc_free(struct mem_ctl_info *mci);
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extern struct mem_ctl_info *edac_mc_find(int idx);
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extern struct mem_ctl_info *find_mci_by_dev(struct device *dev);
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extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
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extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
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unsigned long page);
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/*
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* The no info errors are used when error overflows are reported.
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* There are a limited number of error logging registers that can
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* be exausted. When all registers are exhausted and an additional
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* error occurs then an error overflow register records that an
|
|
* error occurred and the type of error, but doesn't have any
|
|
* further information. The ce/ue versions make for cleaner
|
|
* reporting logic and function interface - reduces conditional
|
|
* statement clutter and extra function arguments.
|
|
*/
|
|
|
|
void edac_mc_handle_error(const enum hw_event_mc_err_type type,
|
|
struct mem_ctl_info *mci,
|
|
const unsigned long page_frame_number,
|
|
const unsigned long offset_in_page,
|
|
const unsigned long syndrome,
|
|
const int layer0,
|
|
const int layer1,
|
|
const int layer2,
|
|
const char *msg,
|
|
const char *other_detail,
|
|
const void *mcelog);
|
|
|
|
static inline void edac_mc_handle_ce(struct mem_ctl_info *mci,
|
|
unsigned long page_frame_number,
|
|
unsigned long offset_in_page,
|
|
unsigned long syndrome, int row, int channel,
|
|
const char *msg)
|
|
{
|
|
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
|
|
page_frame_number, offset_in_page, syndrome,
|
|
row, channel, -1, msg, NULL, NULL);
|
|
}
|
|
|
|
static inline void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
|
|
const char *msg)
|
|
{
|
|
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
|
|
0, 0, 0, -1, -1, -1, msg, NULL, NULL);
|
|
}
|
|
|
|
static inline void edac_mc_handle_ue(struct mem_ctl_info *mci,
|
|
unsigned long page_frame_number,
|
|
unsigned long offset_in_page, int row,
|
|
const char *msg)
|
|
{
|
|
edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
|
|
page_frame_number, offset_in_page, 0,
|
|
row, -1, -1, msg, NULL, NULL);
|
|
}
|
|
|
|
static inline void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
|
|
const char *msg)
|
|
{
|
|
edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
|
|
0, 0, 0, -1, -1, -1, msg, NULL, NULL);
|
|
}
|
|
|
|
static inline void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci,
|
|
unsigned int csrow,
|
|
unsigned int channel0,
|
|
unsigned int channel1,
|
|
char *msg)
|
|
{
|
|
/*
|
|
*FIXME: The error can also be at channel1 (e. g. at the second
|
|
* channel of the same branch). The fix is to push
|
|
* edac_mc_handle_error() call into each driver
|
|
*/
|
|
edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
|
|
0, 0, 0,
|
|
csrow, channel0, -1, msg, NULL, NULL);
|
|
}
|
|
|
|
static inline void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci,
|
|
unsigned int csrow,
|
|
unsigned int channel, char *msg)
|
|
{
|
|
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
|
|
0, 0, 0,
|
|
csrow, channel, -1, msg, NULL, NULL);
|
|
}
|
|
|
|
/*
|
|
* edac_device APIs
|
|
*/
|
|
extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
|
|
extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
|
|
extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
|
|
int inst_nr, int block_nr, const char *msg);
|
|
extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
|
|
int inst_nr, int block_nr, const char *msg);
|
|
extern int edac_device_alloc_index(void);
|
|
extern const char *edac_layer_name[];
|
|
|
|
/*
|
|
* edac_pci APIs
|
|
*/
|
|
extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
|
|
const char *edac_pci_name);
|
|
|
|
extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
|
|
|
|
extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
|
|
unsigned long value);
|
|
|
|
extern int edac_pci_alloc_index(void);
|
|
extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
|
|
extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
|
|
|
|
extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
|
|
struct device *dev,
|
|
const char *mod_name);
|
|
|
|
extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
|
|
extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
|
|
extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
|
|
|
|
/*
|
|
* edac misc APIs
|
|
*/
|
|
extern char *edac_op_state_to_string(int op_state);
|
|
|
|
#endif /* _EDAC_CORE_H_ */
|