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914b32f65a
When the SMI address of the switch chip is zero, the chip assumes to be the only one on the SMI master bus and thus responds to all its known SMI devices addresses (port registers, Global2, etc.) When its SMI address is not zero, some chips (e.g. 88E6352) use an indirect access through two SMI Command and Data registers. Other models (e.g. 88E6060) using less than 16 internal SMI addresses always use a direct access. Add a capability flag to describe chips supporting the (indirect) Multi-chip Addressing Mode, and a low-level API to access the registers via SMI. Other accesses (like Ethernet management frames) may be added later. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| b53 | ||
| bcm_sf2_regs.h | ||
| bcm_sf2.c | ||
| bcm_sf2.h | ||
| Kconfig | ||
| Makefile | ||
| mv88e6xxx.c | ||
| mv88e6xxx.h | ||
| mv88e6060.c | ||
| mv88e6060.h | ||