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126ae9adc1
The default cache operations for ARM64 were changed during 3.15. To use coherent operations a "dma-coherent" device tree property is required. If that property is not present in the device tree node then the non-coherent operations are assigned for the device. Add support to the ccp driver to assign the AXI DMA cache settings based on whether the "dma-coherent" property is present in the device node. If present, use settings that work with the caches. If not present, use settings that do not look at the caches. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
643 lines
14 KiB
C
643 lines
14 KiB
C
/*
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* AMD Cryptographic Coprocessor (CCP) driver
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*
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* Copyright (C) 2013 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/kthread.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/hw_random.h>
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#include <linux/cpu.h>
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#ifdef CONFIG_X86
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#include <asm/cpu_device_id.h>
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#endif
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#include <linux/ccp.h>
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#include "ccp-dev.h"
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MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
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MODULE_LICENSE("GPL");
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MODULE_VERSION("1.0.0");
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MODULE_DESCRIPTION("AMD Cryptographic Coprocessor driver");
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struct ccp_tasklet_data {
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struct completion completion;
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struct ccp_cmd *cmd;
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};
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static struct ccp_device *ccp_dev;
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static inline struct ccp_device *ccp_get_device(void)
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{
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return ccp_dev;
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}
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static inline void ccp_add_device(struct ccp_device *ccp)
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{
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ccp_dev = ccp;
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}
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static inline void ccp_del_device(struct ccp_device *ccp)
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{
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ccp_dev = NULL;
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}
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/**
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* ccp_enqueue_cmd - queue an operation for processing by the CCP
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*
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* @cmd: ccp_cmd struct to be processed
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*
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* Queue a cmd to be processed by the CCP. If queueing the cmd
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* would exceed the defined length of the cmd queue the cmd will
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* only be queued if the CCP_CMD_MAY_BACKLOG flag is set and will
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* result in a return code of -EBUSY.
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*
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* The callback routine specified in the ccp_cmd struct will be
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* called to notify the caller of completion (if the cmd was not
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* backlogged) or advancement out of the backlog. If the cmd has
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* advanced out of the backlog the "err" value of the callback
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* will be -EINPROGRESS. Any other "err" value during callback is
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* the result of the operation.
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*
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* The cmd has been successfully queued if:
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* the return code is -EINPROGRESS or
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* the return code is -EBUSY and CCP_CMD_MAY_BACKLOG flag is set
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*/
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int ccp_enqueue_cmd(struct ccp_cmd *cmd)
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{
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struct ccp_device *ccp = ccp_get_device();
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unsigned long flags;
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unsigned int i;
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int ret;
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if (!ccp)
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return -ENODEV;
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/* Caller must supply a callback routine */
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if (!cmd->callback)
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return -EINVAL;
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cmd->ccp = ccp;
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spin_lock_irqsave(&ccp->cmd_lock, flags);
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i = ccp->cmd_q_count;
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if (ccp->cmd_count >= MAX_CMD_QLEN) {
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ret = -EBUSY;
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if (cmd->flags & CCP_CMD_MAY_BACKLOG)
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list_add_tail(&cmd->entry, &ccp->backlog);
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} else {
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ret = -EINPROGRESS;
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ccp->cmd_count++;
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list_add_tail(&cmd->entry, &ccp->cmd);
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/* Find an idle queue */
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if (!ccp->suspending) {
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for (i = 0; i < ccp->cmd_q_count; i++) {
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if (ccp->cmd_q[i].active)
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continue;
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break;
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}
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}
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}
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spin_unlock_irqrestore(&ccp->cmd_lock, flags);
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/* If we found an idle queue, wake it up */
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if (i < ccp->cmd_q_count)
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wake_up_process(ccp->cmd_q[i].kthread);
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return ret;
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}
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EXPORT_SYMBOL_GPL(ccp_enqueue_cmd);
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static void ccp_do_cmd_backlog(struct work_struct *work)
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{
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struct ccp_cmd *cmd = container_of(work, struct ccp_cmd, work);
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struct ccp_device *ccp = cmd->ccp;
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unsigned long flags;
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unsigned int i;
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cmd->callback(cmd->data, -EINPROGRESS);
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spin_lock_irqsave(&ccp->cmd_lock, flags);
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ccp->cmd_count++;
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list_add_tail(&cmd->entry, &ccp->cmd);
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/* Find an idle queue */
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for (i = 0; i < ccp->cmd_q_count; i++) {
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if (ccp->cmd_q[i].active)
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continue;
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break;
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}
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spin_unlock_irqrestore(&ccp->cmd_lock, flags);
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/* If we found an idle queue, wake it up */
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if (i < ccp->cmd_q_count)
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wake_up_process(ccp->cmd_q[i].kthread);
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}
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static struct ccp_cmd *ccp_dequeue_cmd(struct ccp_cmd_queue *cmd_q)
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{
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struct ccp_device *ccp = cmd_q->ccp;
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struct ccp_cmd *cmd = NULL;
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struct ccp_cmd *backlog = NULL;
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unsigned long flags;
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spin_lock_irqsave(&ccp->cmd_lock, flags);
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cmd_q->active = 0;
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if (ccp->suspending) {
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cmd_q->suspended = 1;
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spin_unlock_irqrestore(&ccp->cmd_lock, flags);
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wake_up_interruptible(&ccp->suspend_queue);
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return NULL;
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}
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if (ccp->cmd_count) {
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cmd_q->active = 1;
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cmd = list_first_entry(&ccp->cmd, struct ccp_cmd, entry);
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list_del(&cmd->entry);
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ccp->cmd_count--;
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}
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if (!list_empty(&ccp->backlog)) {
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backlog = list_first_entry(&ccp->backlog, struct ccp_cmd,
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entry);
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list_del(&backlog->entry);
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}
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spin_unlock_irqrestore(&ccp->cmd_lock, flags);
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if (backlog) {
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INIT_WORK(&backlog->work, ccp_do_cmd_backlog);
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schedule_work(&backlog->work);
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}
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return cmd;
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}
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static void ccp_do_cmd_complete(unsigned long data)
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{
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struct ccp_tasklet_data *tdata = (struct ccp_tasklet_data *)data;
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struct ccp_cmd *cmd = tdata->cmd;
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cmd->callback(cmd->data, cmd->ret);
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complete(&tdata->completion);
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}
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static int ccp_cmd_queue_thread(void *data)
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{
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struct ccp_cmd_queue *cmd_q = (struct ccp_cmd_queue *)data;
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struct ccp_cmd *cmd;
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struct ccp_tasklet_data tdata;
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struct tasklet_struct tasklet;
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tasklet_init(&tasklet, ccp_do_cmd_complete, (unsigned long)&tdata);
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set_current_state(TASK_INTERRUPTIBLE);
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while (!kthread_should_stop()) {
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schedule();
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set_current_state(TASK_INTERRUPTIBLE);
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cmd = ccp_dequeue_cmd(cmd_q);
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if (!cmd)
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continue;
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__set_current_state(TASK_RUNNING);
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/* Execute the command */
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cmd->ret = ccp_run_cmd(cmd_q, cmd);
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/* Schedule the completion callback */
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tdata.cmd = cmd;
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init_completion(&tdata.completion);
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tasklet_schedule(&tasklet);
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wait_for_completion(&tdata.completion);
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}
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__set_current_state(TASK_RUNNING);
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return 0;
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}
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static int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait)
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{
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struct ccp_device *ccp = container_of(rng, struct ccp_device, hwrng);
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u32 trng_value;
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int len = min_t(int, sizeof(trng_value), max);
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/*
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* Locking is provided by the caller so we can update device
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* hwrng-related fields safely
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*/
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trng_value = ioread32(ccp->io_regs + TRNG_OUT_REG);
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if (!trng_value) {
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/* Zero is returned if not data is available or if a
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* bad-entropy error is present. Assume an error if
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* we exceed TRNG_RETRIES reads of zero.
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*/
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if (ccp->hwrng_retries++ > TRNG_RETRIES)
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return -EIO;
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return 0;
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}
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/* Reset the counter and save the rng value */
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ccp->hwrng_retries = 0;
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memcpy(data, &trng_value, len);
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return len;
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}
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/**
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* ccp_alloc_struct - allocate and initialize the ccp_device struct
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*
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* @dev: device struct of the CCP
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*/
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struct ccp_device *ccp_alloc_struct(struct device *dev)
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{
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struct ccp_device *ccp;
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ccp = kzalloc(sizeof(*ccp), GFP_KERNEL);
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if (ccp == NULL) {
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dev_err(dev, "unable to allocate device struct\n");
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return NULL;
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}
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ccp->dev = dev;
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INIT_LIST_HEAD(&ccp->cmd);
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INIT_LIST_HEAD(&ccp->backlog);
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spin_lock_init(&ccp->cmd_lock);
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mutex_init(&ccp->req_mutex);
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mutex_init(&ccp->ksb_mutex);
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ccp->ksb_count = KSB_COUNT;
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ccp->ksb_start = 0;
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return ccp;
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}
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/**
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* ccp_init - initialize the CCP device
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*
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* @ccp: ccp_device struct
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*/
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int ccp_init(struct ccp_device *ccp)
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{
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struct device *dev = ccp->dev;
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struct ccp_cmd_queue *cmd_q;
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struct dma_pool *dma_pool;
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char dma_pool_name[MAX_DMAPOOL_NAME_LEN];
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unsigned int qmr, qim, i;
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int ret;
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/* Find available queues */
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qim = 0;
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qmr = ioread32(ccp->io_regs + Q_MASK_REG);
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for (i = 0; i < MAX_HW_QUEUES; i++) {
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if (!(qmr & (1 << i)))
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continue;
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/* Allocate a dma pool for this queue */
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snprintf(dma_pool_name, sizeof(dma_pool_name), "ccp_q%d", i);
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dma_pool = dma_pool_create(dma_pool_name, dev,
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CCP_DMAPOOL_MAX_SIZE,
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CCP_DMAPOOL_ALIGN, 0);
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if (!dma_pool) {
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dev_err(dev, "unable to allocate dma pool\n");
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ret = -ENOMEM;
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goto e_pool;
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}
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cmd_q = &ccp->cmd_q[ccp->cmd_q_count];
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ccp->cmd_q_count++;
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cmd_q->ccp = ccp;
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cmd_q->id = i;
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cmd_q->dma_pool = dma_pool;
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/* Reserve 2 KSB regions for the queue */
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cmd_q->ksb_key = KSB_START + ccp->ksb_start++;
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cmd_q->ksb_ctx = KSB_START + ccp->ksb_start++;
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ccp->ksb_count -= 2;
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/* Preset some register values and masks that are queue
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* number dependent
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*/
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cmd_q->reg_status = ccp->io_regs + CMD_Q_STATUS_BASE +
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(CMD_Q_STATUS_INCR * i);
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cmd_q->reg_int_status = ccp->io_regs + CMD_Q_INT_STATUS_BASE +
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(CMD_Q_STATUS_INCR * i);
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cmd_q->int_ok = 1 << (i * 2);
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cmd_q->int_err = 1 << ((i * 2) + 1);
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cmd_q->free_slots = CMD_Q_DEPTH(ioread32(cmd_q->reg_status));
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init_waitqueue_head(&cmd_q->int_queue);
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/* Build queue interrupt mask (two interrupts per queue) */
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qim |= cmd_q->int_ok | cmd_q->int_err;
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#ifdef CONFIG_ARM64
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/* For arm64 set the recommended queue cache settings */
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iowrite32(ccp->axcache, ccp->io_regs + CMD_Q_CACHE_BASE +
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(CMD_Q_CACHE_INC * i));
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#endif
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dev_dbg(dev, "queue #%u available\n", i);
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}
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if (ccp->cmd_q_count == 0) {
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dev_notice(dev, "no command queues available\n");
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ret = -EIO;
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goto e_pool;
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}
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dev_notice(dev, "%u command queues available\n", ccp->cmd_q_count);
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/* Disable and clear interrupts until ready */
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iowrite32(0x00, ccp->io_regs + IRQ_MASK_REG);
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for (i = 0; i < ccp->cmd_q_count; i++) {
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cmd_q = &ccp->cmd_q[i];
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ioread32(cmd_q->reg_int_status);
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ioread32(cmd_q->reg_status);
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}
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iowrite32(qim, ccp->io_regs + IRQ_STATUS_REG);
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/* Request an irq */
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ret = ccp->get_irq(ccp);
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if (ret) {
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dev_err(dev, "unable to allocate an IRQ\n");
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goto e_pool;
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}
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/* Initialize the queues used to wait for KSB space and suspend */
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init_waitqueue_head(&ccp->ksb_queue);
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init_waitqueue_head(&ccp->suspend_queue);
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/* Create a kthread for each queue */
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for (i = 0; i < ccp->cmd_q_count; i++) {
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struct task_struct *kthread;
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cmd_q = &ccp->cmd_q[i];
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kthread = kthread_create(ccp_cmd_queue_thread, cmd_q,
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"ccp-q%u", cmd_q->id);
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if (IS_ERR(kthread)) {
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dev_err(dev, "error creating queue thread (%ld)\n",
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PTR_ERR(kthread));
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ret = PTR_ERR(kthread);
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goto e_kthread;
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}
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cmd_q->kthread = kthread;
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wake_up_process(kthread);
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}
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/* Register the RNG */
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ccp->hwrng.name = "ccp-rng";
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ccp->hwrng.read = ccp_trng_read;
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ret = hwrng_register(&ccp->hwrng);
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if (ret) {
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dev_err(dev, "error registering hwrng (%d)\n", ret);
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goto e_kthread;
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}
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/* Make the device struct available before enabling interrupts */
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ccp_add_device(ccp);
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/* Enable interrupts */
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iowrite32(qim, ccp->io_regs + IRQ_MASK_REG);
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return 0;
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e_kthread:
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for (i = 0; i < ccp->cmd_q_count; i++)
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if (ccp->cmd_q[i].kthread)
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kthread_stop(ccp->cmd_q[i].kthread);
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ccp->free_irq(ccp);
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e_pool:
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for (i = 0; i < ccp->cmd_q_count; i++)
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dma_pool_destroy(ccp->cmd_q[i].dma_pool);
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return ret;
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}
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/**
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* ccp_destroy - tear down the CCP device
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*
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* @ccp: ccp_device struct
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*/
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void ccp_destroy(struct ccp_device *ccp)
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{
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struct ccp_cmd_queue *cmd_q;
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struct ccp_cmd *cmd;
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unsigned int qim, i;
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/* Remove general access to the device struct */
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ccp_del_device(ccp);
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/* Unregister the RNG */
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hwrng_unregister(&ccp->hwrng);
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/* Stop the queue kthreads */
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for (i = 0; i < ccp->cmd_q_count; i++)
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if (ccp->cmd_q[i].kthread)
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kthread_stop(ccp->cmd_q[i].kthread);
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/* Build queue interrupt mask (two interrupt masks per queue) */
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qim = 0;
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for (i = 0; i < ccp->cmd_q_count; i++) {
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cmd_q = &ccp->cmd_q[i];
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qim |= cmd_q->int_ok | cmd_q->int_err;
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}
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/* Disable and clear interrupts */
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iowrite32(0x00, ccp->io_regs + IRQ_MASK_REG);
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for (i = 0; i < ccp->cmd_q_count; i++) {
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cmd_q = &ccp->cmd_q[i];
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ioread32(cmd_q->reg_int_status);
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ioread32(cmd_q->reg_status);
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}
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iowrite32(qim, ccp->io_regs + IRQ_STATUS_REG);
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ccp->free_irq(ccp);
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for (i = 0; i < ccp->cmd_q_count; i++)
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dma_pool_destroy(ccp->cmd_q[i].dma_pool);
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/* Flush the cmd and backlog queue */
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while (!list_empty(&ccp->cmd)) {
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/* Invoke the callback directly with an error code */
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cmd = list_first_entry(&ccp->cmd, struct ccp_cmd, entry);
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list_del(&cmd->entry);
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cmd->callback(cmd->data, -ENODEV);
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}
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while (!list_empty(&ccp->backlog)) {
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/* Invoke the callback directly with an error code */
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cmd = list_first_entry(&ccp->backlog, struct ccp_cmd, entry);
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|
list_del(&cmd->entry);
|
|
cmd->callback(cmd->data, -ENODEV);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ccp_irq_handler - handle interrupts generated by the CCP device
|
|
*
|
|
* @irq: the irq associated with the interrupt
|
|
* @data: the data value supplied when the irq was created
|
|
*/
|
|
irqreturn_t ccp_irq_handler(int irq, void *data)
|
|
{
|
|
struct device *dev = data;
|
|
struct ccp_device *ccp = dev_get_drvdata(dev);
|
|
struct ccp_cmd_queue *cmd_q;
|
|
u32 q_int, status;
|
|
unsigned int i;
|
|
|
|
status = ioread32(ccp->io_regs + IRQ_STATUS_REG);
|
|
|
|
for (i = 0; i < ccp->cmd_q_count; i++) {
|
|
cmd_q = &ccp->cmd_q[i];
|
|
|
|
q_int = status & (cmd_q->int_ok | cmd_q->int_err);
|
|
if (q_int) {
|
|
cmd_q->int_status = status;
|
|
cmd_q->q_status = ioread32(cmd_q->reg_status);
|
|
cmd_q->q_int_status = ioread32(cmd_q->reg_int_status);
|
|
|
|
/* On error, only save the first error value */
|
|
if ((q_int & cmd_q->int_err) && !cmd_q->cmd_error)
|
|
cmd_q->cmd_error = CMD_Q_ERROR(cmd_q->q_status);
|
|
|
|
cmd_q->int_rcvd = 1;
|
|
|
|
/* Acknowledge the interrupt and wake the kthread */
|
|
iowrite32(q_int, ccp->io_regs + IRQ_STATUS_REG);
|
|
wake_up_interruptible(&cmd_q->int_queue);
|
|
}
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
bool ccp_queues_suspended(struct ccp_device *ccp)
|
|
{
|
|
unsigned int suspended = 0;
|
|
unsigned long flags;
|
|
unsigned int i;
|
|
|
|
spin_lock_irqsave(&ccp->cmd_lock, flags);
|
|
|
|
for (i = 0; i < ccp->cmd_q_count; i++)
|
|
if (ccp->cmd_q[i].suspended)
|
|
suspended++;
|
|
|
|
spin_unlock_irqrestore(&ccp->cmd_lock, flags);
|
|
|
|
return ccp->cmd_q_count == suspended;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_X86
|
|
static const struct x86_cpu_id ccp_support[] = {
|
|
{ X86_VENDOR_AMD, 22, },
|
|
};
|
|
#endif
|
|
|
|
static int __init ccp_mod_init(void)
|
|
{
|
|
#ifdef CONFIG_X86
|
|
struct cpuinfo_x86 *cpuinfo = &boot_cpu_data;
|
|
int ret;
|
|
|
|
if (!x86_match_cpu(ccp_support))
|
|
return -ENODEV;
|
|
|
|
switch (cpuinfo->x86) {
|
|
case 22:
|
|
if ((cpuinfo->x86_model < 48) || (cpuinfo->x86_model > 63))
|
|
return -ENODEV;
|
|
|
|
ret = ccp_pci_init();
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Don't leave the driver loaded if init failed */
|
|
if (!ccp_get_device()) {
|
|
ccp_pci_exit();
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
|
|
break;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM64
|
|
int ret;
|
|
|
|
ret = ccp_platform_init();
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Don't leave the driver loaded if init failed */
|
|
if (!ccp_get_device()) {
|
|
ccp_platform_exit();
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
#endif
|
|
|
|
return -ENODEV;
|
|
}
|
|
|
|
static void __exit ccp_mod_exit(void)
|
|
{
|
|
#ifdef CONFIG_X86
|
|
struct cpuinfo_x86 *cpuinfo = &boot_cpu_data;
|
|
|
|
switch (cpuinfo->x86) {
|
|
case 22:
|
|
ccp_pci_exit();
|
|
break;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM64
|
|
ccp_platform_exit();
|
|
#endif
|
|
}
|
|
|
|
module_init(ccp_mod_init);
|
|
module_exit(ccp_mod_exit);
|