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40dbf6ee38
- Remove dsgl support - doesn't work in T4. - Wrap the immediate PBL as needed when building it in the wr. - Adjust max pbl depth allowed based on ulptx alignment requirements. - Bump the slots per SQ to 5 to allow up to 128MB fast registers. - Advertise fastreg support by default. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com> |
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amso1100 | ||
cxgb3 | ||
cxgb4 | ||
ehca | ||
ipath | ||
mlx4 | ||
mthca | ||
nes | ||
qib |