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35b137630f
VPU stands for Versatile Processing Unit and it's a CPU-integrated
inference accelerator for Computer Vision and Deep Learning
applications.
The VPU device consist of following components:
- Buttress - provides CPU to VPU integration, interrupt, frequency and
power management.
- Memory Management Unit (based on ARM MMU-600) - translates VPU to
host DMA addresses, isolates user workloads.
- RISC based microcontroller - executes firmware that provides job
execution API for the kernel-mode driver
- Neural Compute Subsystem (NCS) - does the actual work, provides
Compute and Copy engines.
- Network on Chip (NoC) - network fabric connecting all the components
This driver supports VPU IP v2.7 integrated into Intel Meteor Lake
client CPUs (14th generation).
Module sources are at drivers/accel/ivpu and module name is
"intel_vpu.ko".
This patch includes only very besic functionality:
- module, PCI device and IRQ initialization
- register definitions and low level register manipulation functions
- SET/GET_PARAM ioctls
- power up without firmware
Co-developed-by: Krystian Pradzynski <krystian.pradzynski@linux.intel.com>
Signed-off-by: Krystian Pradzynski <krystian.pradzynski@linux.intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20230117092723.60441-2-jacek.lawrynowicz@linux.intel.com
171 lines
4.2 KiB
C
171 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020-2023 Intel Corporation
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*/
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#ifndef __IVPU_HW_H__
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#define __IVPU_HW_H__
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#include "ivpu_drv.h"
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struct ivpu_hw_ops {
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int (*info_init)(struct ivpu_device *vdev);
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int (*power_up)(struct ivpu_device *vdev);
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int (*boot_fw)(struct ivpu_device *vdev);
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int (*power_down)(struct ivpu_device *vdev);
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bool (*is_idle)(struct ivpu_device *vdev);
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void (*wdt_disable)(struct ivpu_device *vdev);
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void (*diagnose_failure)(struct ivpu_device *vdev);
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u32 (*reg_pll_freq_get)(struct ivpu_device *vdev);
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u32 (*reg_telemetry_offset_get)(struct ivpu_device *vdev);
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u32 (*reg_telemetry_size_get)(struct ivpu_device *vdev);
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u32 (*reg_telemetry_enable_get)(struct ivpu_device *vdev);
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void (*reg_db_set)(struct ivpu_device *vdev, u32 db_id);
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u32 (*reg_ipc_rx_addr_get)(struct ivpu_device *vdev);
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u32 (*reg_ipc_rx_count_get)(struct ivpu_device *vdev);
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void (*reg_ipc_tx_set)(struct ivpu_device *vdev, u32 vpu_addr);
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void (*irq_clear)(struct ivpu_device *vdev);
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void (*irq_enable)(struct ivpu_device *vdev);
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void (*irq_disable)(struct ivpu_device *vdev);
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irqreturn_t (*irq_handler)(int irq, void *ptr);
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};
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struct ivpu_addr_range {
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resource_size_t start;
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resource_size_t end;
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};
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struct ivpu_hw_info {
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const struct ivpu_hw_ops *ops;
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struct {
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struct ivpu_addr_range global_low;
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struct ivpu_addr_range global_high;
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struct ivpu_addr_range user_low;
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struct ivpu_addr_range user_high;
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struct ivpu_addr_range global_aliased_pio;
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} ranges;
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struct {
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u8 min_ratio;
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u8 max_ratio;
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/*
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* Pll ratio for the efficiency frequency. The VPU has optimum
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* performance to power ratio at this frequency.
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*/
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u8 pn_ratio;
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u32 profiling_freq;
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} pll;
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u32 tile_fuse;
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u32 sku;
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u16 config;
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};
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extern const struct ivpu_hw_ops ivpu_hw_mtl_ops;
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static inline int ivpu_hw_info_init(struct ivpu_device *vdev)
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{
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return vdev->hw->ops->info_init(vdev);
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};
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static inline int ivpu_hw_power_up(struct ivpu_device *vdev)
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{
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ivpu_dbg(vdev, PM, "HW power up\n");
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return vdev->hw->ops->power_up(vdev);
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};
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static inline int ivpu_hw_boot_fw(struct ivpu_device *vdev)
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{
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return vdev->hw->ops->boot_fw(vdev);
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};
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static inline bool ivpu_hw_is_idle(struct ivpu_device *vdev)
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{
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return vdev->hw->ops->is_idle(vdev);
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};
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static inline int ivpu_hw_power_down(struct ivpu_device *vdev)
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{
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ivpu_dbg(vdev, PM, "HW power down\n");
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return vdev->hw->ops->power_down(vdev);
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};
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static inline void ivpu_hw_wdt_disable(struct ivpu_device *vdev)
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{
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vdev->hw->ops->wdt_disable(vdev);
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};
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/* Register indirect accesses */
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static inline u32 ivpu_hw_reg_pll_freq_get(struct ivpu_device *vdev)
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{
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return vdev->hw->ops->reg_pll_freq_get(vdev);
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};
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static inline u32 ivpu_hw_reg_telemetry_offset_get(struct ivpu_device *vdev)
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{
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return vdev->hw->ops->reg_telemetry_offset_get(vdev);
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};
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static inline u32 ivpu_hw_reg_telemetry_size_get(struct ivpu_device *vdev)
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{
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return vdev->hw->ops->reg_telemetry_size_get(vdev);
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};
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static inline u32 ivpu_hw_reg_telemetry_enable_get(struct ivpu_device *vdev)
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{
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return vdev->hw->ops->reg_telemetry_enable_get(vdev);
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};
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static inline void ivpu_hw_reg_db_set(struct ivpu_device *vdev, u32 db_id)
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{
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vdev->hw->ops->reg_db_set(vdev, db_id);
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};
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static inline u32 ivpu_hw_reg_ipc_rx_addr_get(struct ivpu_device *vdev)
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{
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return vdev->hw->ops->reg_ipc_rx_addr_get(vdev);
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};
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static inline u32 ivpu_hw_reg_ipc_rx_count_get(struct ivpu_device *vdev)
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{
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return vdev->hw->ops->reg_ipc_rx_count_get(vdev);
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};
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static inline void ivpu_hw_reg_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
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{
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vdev->hw->ops->reg_ipc_tx_set(vdev, vpu_addr);
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};
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static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev)
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{
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vdev->hw->ops->irq_clear(vdev);
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};
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static inline void ivpu_hw_irq_enable(struct ivpu_device *vdev)
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{
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vdev->hw->ops->irq_enable(vdev);
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};
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static inline void ivpu_hw_irq_disable(struct ivpu_device *vdev)
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{
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vdev->hw->ops->irq_disable(vdev);
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};
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static inline void ivpu_hw_init_range(struct ivpu_addr_range *range, u64 start, u64 size)
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{
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range->start = start;
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range->end = start + size;
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}
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static inline u64 ivpu_hw_range_size(const struct ivpu_addr_range *range)
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{
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return range->end - range->start;
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}
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static inline void ivpu_hw_diagnose_failure(struct ivpu_device *vdev)
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{
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vdev->hw->ops->diagnose_failure(vdev);
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}
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#endif /* __IVPU_HW_H__ */
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