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0a0300dc8c
Most machine classes want some way to register a block of clk_lookup structures, and most do it by implementing a clks_register() type function which walks an array, or by open-coding a loop. Consolidate all this into clkdev_add_table(). Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Kevin Hilman <khilman@deeprootsystems.com> Acked-by: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
641 lines
14 KiB
C
641 lines
14 KiB
C
#include <linux/clk.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <mach/clock.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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#include <asm/clkdev.h>
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#include <asm/bug.h>
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#include <asm/div64.h>
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#include "crm_regs.h"
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#define CRM_SMALL_DIVIDER(base, name) \
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crm_small_divider(base, \
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base ## _ ## name ## _OFFSET, \
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base ## _ ## name ## _MASK)
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#define CRM_1DIVIDER(base, name) \
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crm_divider(base, \
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base ## _ ## name ## _OFFSET, \
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base ## _ ## name ## _MASK, 1)
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#define CRM_16DIVIDER(base, name) \
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crm_divider(base, \
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base ## _ ## name ## _OFFSET, \
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base ## _ ## name ## _MASK, 16)
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static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
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{
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static const u32 crm_small_dividers[] = {
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2, 3, 4, 5, 6, 8, 10, 12
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};
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u8 idx;
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idx = (__raw_readl(reg) & mask) >> offset;
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if (idx > 7)
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return 1;
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return crm_small_dividers[idx];
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}
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static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
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{
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u32 div;
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div = (__raw_readl(reg) & mask) >> offset;
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return div ? div : z;
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}
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static int _clk_1bit_enable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(clk->enable_reg);
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reg |= 1 << clk->enable_shift;
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__raw_writel(reg, clk->enable_reg);
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return 0;
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}
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static void _clk_1bit_disable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(clk->enable_reg);
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reg &= ~(1 << clk->enable_shift);
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__raw_writel(reg, clk->enable_reg);
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}
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static int _clk_3bit_enable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(clk->enable_reg);
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reg |= 0x7 << clk->enable_shift;
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__raw_writel(reg, clk->enable_reg);
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return 0;
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}
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static void _clk_3bit_disable(struct clk *clk)
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{
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u32 reg;
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reg = __raw_readl(clk->enable_reg);
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reg &= ~(0x7 << clk->enable_shift);
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__raw_writel(reg, clk->enable_reg);
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}
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static unsigned long ckih_rate;
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static unsigned long clk_ckih_get_rate(struct clk *clk)
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{
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return ckih_rate;
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}
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static struct clk ckih_clk = {
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.get_rate = clk_ckih_get_rate,
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};
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static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
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{
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return 2 * clk_get_rate(clk->parent);
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}
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static struct clk ckih_x2_clk = {
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.parent = &ckih_clk,
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.get_rate = clk_ckih_x2_get_rate,
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};
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static unsigned long clk_ckil_get_rate(struct clk *clk)
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{
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return CKIL_CLK_FREQ;
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}
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static struct clk ckil_clk = {
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.get_rate = clk_ckil_get_rate,
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};
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/* plls stuff */
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static struct clk mcu_pll_clk;
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static struct clk dsp_pll_clk;
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static struct clk usb_pll_clk;
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static struct clk *pll_clk(u8 sel)
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{
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switch (sel) {
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case 0:
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return &mcu_pll_clk;
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case 1:
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return &dsp_pll_clk;
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case 2:
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return &usb_pll_clk;
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}
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BUG();
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}
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static void __iomem *pll_base(struct clk *clk)
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{
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if (clk == &mcu_pll_clk)
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return MXC_PLL0_BASE;
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else if (clk == &dsp_pll_clk)
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return MXC_PLL1_BASE;
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else if (clk == &usb_pll_clk)
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return MXC_PLL2_BASE;
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BUG();
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}
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static unsigned long clk_pll_get_rate(struct clk *clk)
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{
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const void __iomem *pllbase;
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unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
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long mfn, mfn_abs, mfd, pdf;
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s64 temp;
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pllbase = pll_base(clk);
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pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
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if (pll_hfsm == 0) {
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dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
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dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
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dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
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} else {
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dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
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dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
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dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
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}
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pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
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mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
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mfi = (mfi <= 5) ? 5 : mfi;
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mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
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mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
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mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
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if (mfn < 0)
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mfn_abs = -mfn;
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else
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mfn_abs = mfn;
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/* XXX: actually this asumes that ckih is fed to pll, but spec says
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* that ckih_x2 is also possible. need to check this out.
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*/
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ref_clk = clk_get_rate(&ckih_clk);
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ref_clk *= 2;
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ref_clk /= pdf + 1;
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temp = (u64) ref_clk * mfn_abs;
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do_div(temp, mfd);
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if (mfn < 0)
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temp = -temp;
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temp += ref_clk * mfi;
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return temp;
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}
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static int clk_pll_enable(struct clk *clk)
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{
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void __iomem *ctl;
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u32 reg;
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ctl = pll_base(clk);
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reg = __raw_readl(ctl);
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reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
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__raw_writel(reg, ctl);
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do {
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reg = __raw_readl(ctl);
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} while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
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return 0;
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}
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static void clk_pll_disable(struct clk *clk)
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{
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void __iomem *ctl;
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u32 reg;
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ctl = pll_base(clk);
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reg = __raw_readl(ctl);
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reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
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__raw_writel(reg, ctl);
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}
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static struct clk mcu_pll_clk = {
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.parent = &ckih_clk,
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.get_rate = clk_pll_get_rate,
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.enable = clk_pll_enable,
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.disable = clk_pll_disable,
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};
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static struct clk dsp_pll_clk = {
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.parent = &ckih_clk,
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.get_rate = clk_pll_get_rate,
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.enable = clk_pll_enable,
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.disable = clk_pll_disable,
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};
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static struct clk usb_pll_clk = {
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.parent = &ckih_clk,
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.get_rate = clk_pll_get_rate,
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.enable = clk_pll_enable,
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.disable = clk_pll_disable,
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};
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/* plls stuff end */
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/* ap_ref_clk stuff */
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static struct clk ap_ref_clk;
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static unsigned long clk_ap_ref_get_rate(struct clk *clk)
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{
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u32 ascsr, acsr;
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u8 ap_pat_ref_div_2, ap_isel, acs, ads;
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ascsr = __raw_readl(MXC_CRMAP_ASCSR);
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acsr = __raw_readl(MXC_CRMAP_ACSR);
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/* 0 for ckih, 1 for ckih*2 */
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ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
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/* reg divider */
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ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
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/* undocumented, 1 for disabling divider */
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ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
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/* 0 for pat_ref, 1 for divider out */
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acs = acsr & MXC_CRMAP_ACSR_ACS;
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if (acs & !ads)
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/* use divided clock */
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return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);
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return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
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}
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static struct clk ap_ref_clk = {
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.parent = &ckih_clk,
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.get_rate = clk_ap_ref_get_rate,
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};
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/* ap_ref_clk stuff end */
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/* ap_pre_dfs_clk stuff */
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static struct clk ap_pre_dfs_clk;
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static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
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{
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u32 acsr, ascsr;
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acsr = __raw_readl(MXC_CRMAP_ACSR);
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ascsr = __raw_readl(MXC_CRMAP_ASCSR);
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if (acsr & MXC_CRMAP_ACSR_ACS) {
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u8 sel;
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sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
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MXC_CRMAP_ASCSR_APSEL_OFFSET;
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return clk_get_rate(pll_clk(sel)) /
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CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
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}
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return clk_get_rate(&ap_ref_clk);
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}
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static struct clk ap_pre_dfs_clk = {
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.get_rate = clk_ap_pre_dfs_get_rate,
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};
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/* ap_pre_dfs_clk stuff end */
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/* usb_clk stuff */
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static struct clk usb_clk;
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static struct clk *clk_usb_parent(struct clk *clk)
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{
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u32 acsr, ascsr;
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acsr = __raw_readl(MXC_CRMAP_ACSR);
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ascsr = __raw_readl(MXC_CRMAP_ASCSR);
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if (acsr & MXC_CRMAP_ACSR_ACS) {
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u8 sel;
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sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
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MXC_CRMAP_ASCSR_USBSEL_OFFSET;
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return pll_clk(sel);
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}
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return &ap_ref_clk;
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}
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static unsigned long clk_usb_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) /
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CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
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}
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static struct clk usb_clk = {
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.enable_reg = MXC_CRMAP_ACDER2,
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.enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
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.get_rate = clk_usb_get_rate,
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.enable = _clk_1bit_enable,
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.disable = _clk_1bit_disable,
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};
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/* usb_clk stuff end */
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static unsigned long clk_ipg_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
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}
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static unsigned long clk_ahb_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) /
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CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
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}
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static struct clk ipg_clk = {
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.parent = &ap_pre_dfs_clk,
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.get_rate = clk_ipg_get_rate,
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};
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static struct clk ahb_clk = {
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.parent = &ap_pre_dfs_clk,
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.get_rate = clk_ahb_get_rate,
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};
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/* perclk_clk stuff */
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static struct clk perclk_clk;
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static unsigned long clk_perclk_get_rate(struct clk *clk)
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{
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u32 acder2;
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acder2 = __raw_readl(MXC_CRMAP_ACDER2);
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if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
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return 2 * clk_get_rate(clk->parent);
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return clk_get_rate(clk->parent);
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}
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static struct clk perclk_clk = {
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.parent = &ckih_clk,
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.get_rate = clk_perclk_get_rate,
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};
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/* perclk_clk stuff end */
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/* uart_clk stuff */
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static struct clk uart_clk[];
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static unsigned long clk_uart_get_rate(struct clk *clk)
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{
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u32 div;
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switch (clk->id) {
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case 0:
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case 1:
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div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
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break;
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case 2:
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div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
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break;
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default:
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BUG();
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}
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return clk_get_rate(clk->parent) / div;
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}
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static struct clk uart_clk[] = {
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{
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.id = 0,
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.parent = &perclk_clk,
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.enable_reg = MXC_CRMAP_APRA,
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.enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
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.get_rate = clk_uart_get_rate,
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.enable = _clk_1bit_enable,
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.disable = _clk_1bit_disable,
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}, {
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.id = 1,
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.parent = &perclk_clk,
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.enable_reg = MXC_CRMAP_APRA,
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.enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
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.get_rate = clk_uart_get_rate,
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.enable = _clk_1bit_enable,
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.disable = _clk_1bit_disable,
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}, {
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.id = 2,
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.parent = &perclk_clk,
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.enable_reg = MXC_CRMAP_APRA,
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.enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
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.get_rate = clk_uart_get_rate,
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.enable = _clk_1bit_enable,
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.disable = _clk_1bit_disable,
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},
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};
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/* uart_clk stuff end */
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/* sdhc_clk stuff */
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static struct clk nfc_clk;
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static unsigned long clk_nfc_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) /
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CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
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}
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static struct clk nfc_clk = {
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.parent = &ahb_clk,
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.enable_reg = MXC_CRMAP_ACDER2,
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.enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
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.get_rate = clk_nfc_get_rate,
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.enable = _clk_1bit_enable,
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.disable = _clk_1bit_disable,
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};
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/* sdhc_clk stuff end */
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/* sdhc_clk stuff */
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static struct clk sdhc_clk[];
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static struct clk *clk_sdhc_parent(struct clk *clk)
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{
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u32 aprb;
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u8 sel;
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u32 mask;
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int offset;
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aprb = __raw_readl(MXC_CRMAP_APRB);
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switch (clk->id) {
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case 0:
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mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
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offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
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break;
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case 1:
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mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
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offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
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break;
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default:
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BUG();
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}
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sel = (aprb & mask) >> offset;
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switch (sel) {
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case 0:
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return &ckih_clk;
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case 1:
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return &ckih_x2_clk;
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}
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return &usb_clk;
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}
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static unsigned long clk_sdhc_get_rate(struct clk *clk)
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{
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u32 div;
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switch (clk->id) {
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case 0:
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div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
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break;
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case 1:
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div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
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break;
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default:
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BUG();
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}
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return clk_get_rate(clk->parent) / div;
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}
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static int clk_sdhc_enable(struct clk *clk)
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{
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u32 amlpmre1, aprb;
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amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
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aprb = __raw_readl(MXC_CRMAP_APRB);
|
|
switch (clk->id) {
|
|
case 0:
|
|
amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
|
|
aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
|
|
break;
|
|
case 1:
|
|
amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
|
|
aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
|
|
break;
|
|
}
|
|
__raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
|
|
__raw_writel(aprb, MXC_CRMAP_APRB);
|
|
return 0;
|
|
}
|
|
|
|
static void clk_sdhc_disable(struct clk *clk)
|
|
{
|
|
u32 amlpmre1, aprb;
|
|
|
|
amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
|
|
aprb = __raw_readl(MXC_CRMAP_APRB);
|
|
switch (clk->id) {
|
|
case 0:
|
|
amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
|
|
aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
|
|
break;
|
|
case 1:
|
|
amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
|
|
aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
|
|
break;
|
|
}
|
|
__raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
|
|
__raw_writel(aprb, MXC_CRMAP_APRB);
|
|
}
|
|
|
|
static struct clk sdhc_clk[] = {
|
|
{
|
|
.id = 0,
|
|
.get_rate = clk_sdhc_get_rate,
|
|
.enable = clk_sdhc_enable,
|
|
.disable = clk_sdhc_disable,
|
|
}, {
|
|
.id = 1,
|
|
.get_rate = clk_sdhc_get_rate,
|
|
.enable = clk_sdhc_enable,
|
|
.disable = clk_sdhc_disable,
|
|
},
|
|
};
|
|
/* sdhc_clk stuff end */
|
|
|
|
/* wdog_clk stuff */
|
|
static struct clk wdog_clk[] = {
|
|
{
|
|
.id = 0,
|
|
.parent = &ipg_clk,
|
|
.enable_reg = MXC_CRMAP_AMLPMRD,
|
|
.enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
|
|
.enable = _clk_3bit_enable,
|
|
.disable = _clk_3bit_disable,
|
|
}, {
|
|
.id = 1,
|
|
.parent = &ipg_clk,
|
|
.enable_reg = MXC_CRMAP_AMLPMRD,
|
|
.enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
|
|
.enable = _clk_3bit_enable,
|
|
.disable = _clk_3bit_disable,
|
|
},
|
|
};
|
|
/* wdog_clk stuff end */
|
|
|
|
/* gpt_clk stuff */
|
|
static struct clk gpt_clk = {
|
|
.parent = &ipg_clk,
|
|
.enable_reg = MXC_CRMAP_AMLPMRC,
|
|
.enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
|
|
.enable = _clk_3bit_enable,
|
|
.disable = _clk_3bit_disable,
|
|
};
|
|
/* gpt_clk stuff end */
|
|
|
|
/* cspi_clk stuff */
|
|
static struct clk cspi_clk[] = {
|
|
{
|
|
.id = 0,
|
|
.parent = &ipg_clk,
|
|
.enable_reg = MXC_CRMAP_AMLPMRE2,
|
|
.enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
|
|
.enable = _clk_3bit_enable,
|
|
.disable = _clk_3bit_disable,
|
|
}, {
|
|
.id = 1,
|
|
.parent = &ipg_clk,
|
|
.enable_reg = MXC_CRMAP_AMLPMRE1,
|
|
.enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
|
|
.enable = _clk_3bit_enable,
|
|
.disable = _clk_3bit_disable,
|
|
},
|
|
};
|
|
/* cspi_clk stuff end */
|
|
|
|
#define _REGISTER_CLOCK(d, n, c) \
|
|
{ \
|
|
.dev_id = d, \
|
|
.con_id = n, \
|
|
.clk = &c, \
|
|
},
|
|
|
|
static struct clk_lookup lookups[] = {
|
|
_REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
|
|
_REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
|
|
_REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
|
|
_REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
|
|
_REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
|
|
_REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
|
|
_REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
|
|
_REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
|
|
};
|
|
|
|
int __init mxc91231_clocks_init(unsigned long fref)
|
|
{
|
|
void __iomem *gpt_base;
|
|
|
|
ckih_rate = fref;
|
|
|
|
usb_clk.parent = clk_usb_parent(&usb_clk);
|
|
sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
|
|
sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
|
|
|
|
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
|
|
|
gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
|
|
mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
|
|
|
|
return 0;
|
|
}
|