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93fc9e1bb6
For ethernet support, we need to reserve QPs for the ethernet and fibre channel driver. The QPs are reserved at the end of the QP table. (This way we assure that they are aligned to their size) We need to consider these reserved ranges in bitmap creation, so we extend the mlx4 bitmap utility functions to allow reserved ranges at both the bottom and the top of the range. Signed-off-by: Yevgeny Petrilin <yevgenyp@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
259 lines
6.9 KiB
C
259 lines
6.9 KiB
C
/*
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* Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
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* Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/init.h>
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#include <linux/mlx4/cmd.h>
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#include "mlx4.h"
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#include "icm.h"
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struct mlx4_srq_context {
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__be32 state_logsize_srqn;
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u8 logstride;
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u8 reserved1[3];
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u8 pg_offset;
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u8 reserved2[3];
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u32 reserved3;
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u8 log_page_size;
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u8 reserved4[2];
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u8 mtt_base_addr_h;
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__be32 mtt_base_addr_l;
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__be32 pd;
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__be16 limit_watermark;
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__be16 wqe_cnt;
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u16 reserved5;
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__be16 wqe_counter;
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u32 reserved6;
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__be64 db_rec_addr;
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};
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void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type)
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{
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struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
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struct mlx4_srq *srq;
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spin_lock(&srq_table->lock);
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srq = radix_tree_lookup(&srq_table->tree, srqn & (dev->caps.num_srqs - 1));
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if (srq)
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atomic_inc(&srq->refcount);
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spin_unlock(&srq_table->lock);
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if (!srq) {
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mlx4_warn(dev, "Async event for bogus SRQ %08x\n", srqn);
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return;
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}
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srq->event(srq, event_type);
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if (atomic_dec_and_test(&srq->refcount))
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complete(&srq->free);
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}
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static int mlx4_SW2HW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
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int srq_num)
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{
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return mlx4_cmd(dev, mailbox->dma, srq_num, 0, MLX4_CMD_SW2HW_SRQ,
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MLX4_CMD_TIME_CLASS_A);
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}
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static int mlx4_HW2SW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
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int srq_num)
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{
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return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, srq_num,
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mailbox ? 0 : 1, MLX4_CMD_HW2SW_SRQ,
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MLX4_CMD_TIME_CLASS_A);
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}
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static int mlx4_ARM_SRQ(struct mlx4_dev *dev, int srq_num, int limit_watermark)
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{
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return mlx4_cmd(dev, limit_watermark, srq_num, 0, MLX4_CMD_ARM_SRQ,
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MLX4_CMD_TIME_CLASS_B);
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}
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static int mlx4_QUERY_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
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int srq_num)
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{
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return mlx4_cmd_box(dev, 0, mailbox->dma, srq_num, 0, MLX4_CMD_QUERY_SRQ,
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MLX4_CMD_TIME_CLASS_A);
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}
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int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
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u64 db_rec, struct mlx4_srq *srq)
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{
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struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_srq_context *srq_context;
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u64 mtt_addr;
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int err;
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srq->srqn = mlx4_bitmap_alloc(&srq_table->bitmap);
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if (srq->srqn == -1)
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return -ENOMEM;
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err = mlx4_table_get(dev, &srq_table->table, srq->srqn);
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if (err)
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goto err_out;
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err = mlx4_table_get(dev, &srq_table->cmpt_table, srq->srqn);
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if (err)
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goto err_put;
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spin_lock_irq(&srq_table->lock);
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err = radix_tree_insert(&srq_table->tree, srq->srqn, srq);
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spin_unlock_irq(&srq_table->lock);
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if (err)
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goto err_cmpt_put;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox)) {
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err = PTR_ERR(mailbox);
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goto err_radix;
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}
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srq_context = mailbox->buf;
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memset(srq_context, 0, sizeof *srq_context);
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srq_context->state_logsize_srqn = cpu_to_be32((ilog2(srq->max) << 24) |
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srq->srqn);
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srq_context->logstride = srq->wqe_shift - 4;
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srq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
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mtt_addr = mlx4_mtt_addr(dev, mtt);
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srq_context->mtt_base_addr_h = mtt_addr >> 32;
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srq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
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srq_context->pd = cpu_to_be32(pdn);
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srq_context->db_rec_addr = cpu_to_be64(db_rec);
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err = mlx4_SW2HW_SRQ(dev, mailbox, srq->srqn);
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mlx4_free_cmd_mailbox(dev, mailbox);
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if (err)
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goto err_radix;
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atomic_set(&srq->refcount, 1);
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init_completion(&srq->free);
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return 0;
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err_radix:
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spin_lock_irq(&srq_table->lock);
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radix_tree_delete(&srq_table->tree, srq->srqn);
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spin_unlock_irq(&srq_table->lock);
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err_cmpt_put:
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mlx4_table_put(dev, &srq_table->cmpt_table, srq->srqn);
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err_put:
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mlx4_table_put(dev, &srq_table->table, srq->srqn);
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err_out:
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mlx4_bitmap_free(&srq_table->bitmap, srq->srqn);
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return err;
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}
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EXPORT_SYMBOL_GPL(mlx4_srq_alloc);
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void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq)
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{
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struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
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int err;
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err = mlx4_HW2SW_SRQ(dev, NULL, srq->srqn);
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if (err)
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mlx4_warn(dev, "HW2SW_SRQ failed (%d) for SRQN %06x\n", err, srq->srqn);
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spin_lock_irq(&srq_table->lock);
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radix_tree_delete(&srq_table->tree, srq->srqn);
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spin_unlock_irq(&srq_table->lock);
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if (atomic_dec_and_test(&srq->refcount))
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complete(&srq->free);
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wait_for_completion(&srq->free);
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mlx4_table_put(dev, &srq_table->table, srq->srqn);
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mlx4_bitmap_free(&srq_table->bitmap, srq->srqn);
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}
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EXPORT_SYMBOL_GPL(mlx4_srq_free);
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int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark)
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{
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return mlx4_ARM_SRQ(dev, srq->srqn, limit_watermark);
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}
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EXPORT_SYMBOL_GPL(mlx4_srq_arm);
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int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark)
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{
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_srq_context *srq_context;
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int err;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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srq_context = mailbox->buf;
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err = mlx4_QUERY_SRQ(dev, mailbox, srq->srqn);
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if (err)
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goto err_out;
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*limit_watermark = be16_to_cpu(srq_context->limit_watermark);
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err_out:
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mlx4_free_cmd_mailbox(dev, mailbox);
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return err;
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}
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EXPORT_SYMBOL_GPL(mlx4_srq_query);
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int mlx4_init_srq_table(struct mlx4_dev *dev)
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{
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struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
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int err;
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spin_lock_init(&srq_table->lock);
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INIT_RADIX_TREE(&srq_table->tree, GFP_ATOMIC);
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err = mlx4_bitmap_init(&srq_table->bitmap, dev->caps.num_srqs,
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dev->caps.num_srqs - 1, dev->caps.reserved_srqs, 0);
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if (err)
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return err;
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return 0;
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}
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void mlx4_cleanup_srq_table(struct mlx4_dev *dev)
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{
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mlx4_bitmap_cleanup(&mlx4_priv(dev)->srq_table.bitmap);
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}
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