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dadbe85ac4
Currently single PCI pool used across all CPUs and that doesn't scales up as number of CPU increases, so this patch adds per CPU PCI pool to setup udl and that aligns well from FCoE stack as that already has per CPU exch locking. Adds per CPU PCI alloc setup and free in ixgbe_fcoe_ddp_pools_alloc and ixgbe_fcoe_ddp_pools_free, use CPU specific pool during DDP setup. Re-arranged ixgbe_fcoe struct to have fewer holes along with adding pools ptr using pahole. Signed-off-by: Vasu Dev <vasu.dev@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> |
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| .. | ||
| ixgbe_82598.c | ||
| ixgbe_82599.c | ||
| ixgbe_common.c | ||
| ixgbe_common.h | ||
| ixgbe_dcb_82598.c | ||
| ixgbe_dcb_82598.h | ||
| ixgbe_dcb_82599.c | ||
| ixgbe_dcb_82599.h | ||
| ixgbe_dcb_nl.c | ||
| ixgbe_dcb.c | ||
| ixgbe_dcb.h | ||
| ixgbe_ethtool.c | ||
| ixgbe_fcoe.c | ||
| ixgbe_fcoe.h | ||
| ixgbe_main.c | ||
| ixgbe_mbx.c | ||
| ixgbe_mbx.h | ||
| ixgbe_phy.c | ||
| ixgbe_phy.h | ||
| ixgbe_sriov.c | ||
| ixgbe_sriov.h | ||
| ixgbe_type.h | ||
| ixgbe_x540.c | ||
| ixgbe.h | ||
| Makefile | ||