linux/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml
Arnd Bergmann 44e4a2c756 Memory controller drivers - fixes for v5.18
Issues in v5.18:
 1. Freescale/NXP: fix populating children of Integrated Flash Controller
    DT nodes.
 
 Issues existing before:
 1. Renesas: fix platform-device leak in probe's error path.
 2. Atmel: fix of_node reference leak in probe's error path.
 3. Synopsys: correct the bindings for snps,ddrc-3.80a (interrupts are
    required).
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Merge tag 'memory-controller-drv-fixes-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/fixes

Memory controller drivers - fixes for v5.18

Issues in v5.18:
1. Freescale/NXP: fix populating children of Integrated Flash Controller
   DT nodes.

Issues existing before:
1. Renesas: fix platform-device leak in probe's error path.
2. Atmel: fix of_node reference leak in probe's error path.
3. Synopsys: correct the bindings for snps,ddrc-3.80a (interrupts are
   required).

* tag 'memory-controller-drv-fixes-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: fsl_ifc: populate child nodes of buses and mfd devices
  dt-bindings: memory: snps,ddrc-3.80a compatible also need interrupts
  memory: atmel-ebi: Fix missing of_node_put in atmel_ebi_probe
  memory: renesas-rpc-if: fix platform-device leak in error path

Link: https://lore.kernel.org/r/20220407081448.113208-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-07 13:58:17 +02:00

77 lines
1.6 KiB
YAML

# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys IntelliDDR Multi Protocol memory controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Manish Narani <manish.narani@xilinx.com>
- Michal Simek <michal.simek@xilinx.com>
description: |
The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
32-bit bus width configurations.
The Zynq DDR ECC controller has an optional ECC support in half-bus width
(16-bit) configuration.
These both ECC controllers correct single bit ECC errors and detect double bit
ECC errors.
properties:
compatible:
enum:
- snps,ddrc-3.80a
- xlnx,zynq-ddrc-a05
- xlnx,zynqmp-ddrc-2.40a
interrupts:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- snps,ddrc-3.80a
- xlnx,zynqmp-ddrc-2.40a
then:
required:
- interrupts
else:
properties:
interrupts: false
additionalProperties: false
examples:
- |
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
- |
axi {
#address-cells = <2>;
#size-cells = <2>;
memory-controller@fd070000 {
compatible = "xlnx,zynqmp-ddrc-2.40a";
reg = <0x0 0xfd070000 0x0 0x30000>;
interrupt-parent = <&gic>;
interrupts = <0 112 4>;
};
};