Andre Przywara a3eebcb61f dts: add riscv include prefix link ... The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical die as their R528/T113-s siblings with ARM Cortex-A7 cores. To allow sharing the basic SoC .dtsi files across those two architectures as well, introduce a symlink to the RISC-V DT directory. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230320005249.13403-2-andre.przywara@arm.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>		2023-03-27 22:45:22 +02:00
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arc
arm
arm64
dt-bindings
microblaze
mips
nios2
openrisc
powerpc
riscv	dts: add riscv include prefix link	2023-03-27 22:45:22 +02:00
sh
xtensa