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1f3645bb41
Add the missing 1000Base-X entry to the phy settings table. This was not included because the original code could not cope with more than 32 bits of link mode mask. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
282 lines
6.7 KiB
C
282 lines
6.7 KiB
C
/*
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* Core PHY library, taken from phy.c
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/export.h>
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#include <linux/phy.h>
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const char *phy_speed_to_str(int speed)
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{
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switch (speed) {
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case SPEED_10:
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return "10Mbps";
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case SPEED_100:
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return "100Mbps";
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case SPEED_1000:
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return "1Gbps";
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case SPEED_2500:
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return "2.5Gbps";
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case SPEED_5000:
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return "5Gbps";
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case SPEED_10000:
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return "10Gbps";
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case SPEED_14000:
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return "14Gbps";
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case SPEED_20000:
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return "20Gbps";
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case SPEED_25000:
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return "25Gbps";
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case SPEED_40000:
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return "40Gbps";
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case SPEED_50000:
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return "50Gbps";
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case SPEED_56000:
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return "56Gbps";
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case SPEED_100000:
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return "100Gbps";
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case SPEED_UNKNOWN:
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return "Unknown";
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default:
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return "Unsupported (update phy-core.c)";
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}
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}
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EXPORT_SYMBOL_GPL(phy_speed_to_str);
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const char *phy_duplex_to_str(unsigned int duplex)
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{
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if (duplex == DUPLEX_HALF)
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return "Half";
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if (duplex == DUPLEX_FULL)
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return "Full";
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if (duplex == DUPLEX_UNKNOWN)
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return "Unknown";
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return "Unsupported (update phy-core.c)";
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}
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EXPORT_SYMBOL_GPL(phy_duplex_to_str);
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/* A mapping of all SUPPORTED settings to speed/duplex. This table
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* must be grouped by speed and sorted in descending match priority
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* - iow, descending speed. */
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static const struct phy_setting settings[] = {
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{
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.speed = SPEED_10000,
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.duplex = DUPLEX_FULL,
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.bit = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
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},
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{
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.speed = SPEED_10000,
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.duplex = DUPLEX_FULL,
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.bit = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
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},
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{
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.speed = SPEED_10000,
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.duplex = DUPLEX_FULL,
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.bit = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
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},
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{
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.speed = SPEED_2500,
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.duplex = DUPLEX_FULL,
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.bit = ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
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},
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{
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.speed = SPEED_1000,
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.duplex = DUPLEX_FULL,
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.bit = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
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},
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{
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.speed = SPEED_1000,
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.duplex = DUPLEX_FULL,
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.bit = ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
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},
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{
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.speed = SPEED_1000,
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.duplex = DUPLEX_FULL,
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.bit = ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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},
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{
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.speed = SPEED_1000,
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.duplex = DUPLEX_HALF,
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.bit = ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
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},
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{
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.speed = SPEED_100,
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.duplex = DUPLEX_FULL,
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.bit = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
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},
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{
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.speed = SPEED_100,
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.duplex = DUPLEX_HALF,
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.bit = ETHTOOL_LINK_MODE_100baseT_Half_BIT,
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},
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{
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.speed = SPEED_10,
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.duplex = DUPLEX_FULL,
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.bit = ETHTOOL_LINK_MODE_10baseT_Full_BIT,
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},
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{
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.speed = SPEED_10,
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.duplex = DUPLEX_HALF,
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.bit = ETHTOOL_LINK_MODE_10baseT_Half_BIT,
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},
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};
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/**
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* phy_lookup_setting - lookup a PHY setting
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* @speed: speed to match
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* @duplex: duplex to match
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* @mask: allowed link modes
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* @maxbit: bit size of link modes
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* @exact: an exact match is required
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*
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* Search the settings array for a setting that matches the speed and
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* duplex, and which is supported.
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*
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* If @exact is unset, either an exact match or %NULL for no match will
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* be returned.
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*
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* If @exact is set, an exact match, the fastest supported setting at
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* or below the specified speed, the slowest supported setting, or if
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* they all fail, %NULL will be returned.
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*/
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const struct phy_setting *
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phy_lookup_setting(int speed, int duplex, const unsigned long *mask,
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size_t maxbit, bool exact)
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{
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const struct phy_setting *p, *match = NULL, *last = NULL;
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int i;
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for (i = 0, p = settings; i < ARRAY_SIZE(settings); i++, p++) {
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if (p->bit < maxbit && test_bit(p->bit, mask)) {
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last = p;
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if (p->speed == speed && p->duplex == duplex) {
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/* Exact match for speed and duplex */
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match = p;
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break;
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} else if (!exact) {
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if (!match && p->speed <= speed)
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/* Candidate */
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match = p;
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if (p->speed < speed)
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break;
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}
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}
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}
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if (!match && !exact)
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match = last;
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return match;
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}
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EXPORT_SYMBOL_GPL(phy_lookup_setting);
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size_t phy_speeds(unsigned int *speeds, size_t size,
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unsigned long *mask, size_t maxbit)
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{
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size_t count;
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int i;
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for (i = 0, count = 0; i < ARRAY_SIZE(settings) && count < size; i++)
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if (settings[i].bit < maxbit &&
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test_bit(settings[i].bit, mask) &&
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(count == 0 || speeds[count - 1] != settings[i].speed))
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speeds[count++] = settings[i].speed;
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return count;
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}
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static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,
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u16 regnum)
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{
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/* Write the desired MMD Devad */
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bus->write(bus, phy_addr, MII_MMD_CTRL, devad);
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/* Write the desired MMD register address */
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bus->write(bus, phy_addr, MII_MMD_DATA, regnum);
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/* Select the Function : DATA with no post increment */
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bus->write(bus, phy_addr, MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
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}
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/**
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* phy_read_mmd - Convenience function for reading a register
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* from an MMD on a given PHY.
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* @phydev: The phy_device struct
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* @devad: The MMD to read from (0..31)
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* @regnum: The register on the MMD to read (0..65535)
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*
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* Same rules as for phy_read();
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*/
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int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
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{
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int val;
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if (regnum > (u16)~0 || devad > 32)
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return -EINVAL;
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if (phydev->drv->read_mmd) {
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val = phydev->drv->read_mmd(phydev, devad, regnum);
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} else if (phydev->is_c45) {
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u32 addr = MII_ADDR_C45 | (devad << 16) | (regnum & 0xffff);
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val = mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, addr);
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} else {
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struct mii_bus *bus = phydev->mdio.bus;
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int phy_addr = phydev->mdio.addr;
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mutex_lock(&bus->mdio_lock);
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mmd_phy_indirect(bus, phy_addr, devad, regnum);
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/* Read the content of the MMD's selected register */
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val = bus->read(bus, phy_addr, MII_MMD_DATA);
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mutex_unlock(&bus->mdio_lock);
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}
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return val;
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}
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EXPORT_SYMBOL(phy_read_mmd);
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/**
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* phy_write_mmd - Convenience function for writing a register
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* on an MMD on a given PHY.
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* @phydev: The phy_device struct
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* @devad: The MMD to read from
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* @regnum: The register on the MMD to read
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* @val: value to write to @regnum
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*
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* Same rules as for phy_write();
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*/
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int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
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{
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int ret;
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if (regnum > (u16)~0 || devad > 32)
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return -EINVAL;
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if (phydev->drv->write_mmd) {
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ret = phydev->drv->write_mmd(phydev, devad, regnum, val);
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} else if (phydev->is_c45) {
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u32 addr = MII_ADDR_C45 | (devad << 16) | (regnum & 0xffff);
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ret = mdiobus_write(phydev->mdio.bus, phydev->mdio.addr,
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addr, val);
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} else {
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struct mii_bus *bus = phydev->mdio.bus;
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int phy_addr = phydev->mdio.addr;
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mutex_lock(&bus->mdio_lock);
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mmd_phy_indirect(bus, phy_addr, devad, regnum);
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/* Write the data into MMD's selected register */
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bus->write(bus, phy_addr, MII_MMD_DATA, val);
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mutex_unlock(&bus->mdio_lock);
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ret = 0;
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}
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return ret;
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}
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EXPORT_SYMBOL(phy_write_mmd);
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