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3d2abda02a
The SDHI controller in the RZ/A1 has 2 clock sources per channel and both need to be enabled/disabled for proper operation. This fixes the fact that the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and that all 4 clock sources need to be defined an used. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
58 lines
1.3 KiB
C
58 lines
1.3 KiB
C
/*
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* Copyright (C) 2014 Renesas Solutions Corp.
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* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
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#define __DT_BINDINGS_CLOCK_R7S72100_H__
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#define R7S72100_CLK_PLL 0
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/* MSTP3 */
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#define R7S72100_CLK_MTU2 3
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/* MSTP4 */
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#define R7S72100_CLK_SCIF0 7
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#define R7S72100_CLK_SCIF1 6
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#define R7S72100_CLK_SCIF2 5
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#define R7S72100_CLK_SCIF3 4
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#define R7S72100_CLK_SCIF4 3
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#define R7S72100_CLK_SCIF5 2
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#define R7S72100_CLK_SCIF6 1
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#define R7S72100_CLK_SCIF7 0
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/* MSTP5 */
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#define R7S72100_CLK_OSTM0 1
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#define R7S72100_CLK_OSTM1 0
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/* MSTP7 */
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#define R7S72100_CLK_ETHER 4
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/* MSTP8 */
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#define R7S72100_CLK_MMCIF 4
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/* MSTP9 */
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#define R7S72100_CLK_I2C0 7
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#define R7S72100_CLK_I2C1 6
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#define R7S72100_CLK_I2C2 5
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#define R7S72100_CLK_I2C3 4
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/* MSTP10 */
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#define R7S72100_CLK_SPI0 7
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#define R7S72100_CLK_SPI1 6
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#define R7S72100_CLK_SPI2 5
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#define R7S72100_CLK_SPI3 4
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#define R7S72100_CLK_SPI4 3
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/* MSTP12 */
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#define R7S72100_CLK_SDHI00 3
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#define R7S72100_CLK_SDHI01 2
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#define R7S72100_CLK_SDHI10 1
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#define R7S72100_CLK_SDHI11 0
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#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
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