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egpio is a scheme which allows special power Island Domain IOs (LPASS,SSC) to be reused as regular chip GPIOs by muxing regular TLMM functions with Island Domain functions. With this scheme, an IO can be controlled both by the cpu running linux and the Island processor. This provides great flexibility to re-purpose the Island IOs for regular TLMM usecases. 2 new bits are added to ctl_reg, egpio_present is a read only bit which shows if egpio feature is available or not on a given gpio. egpio_enable is the read/write bit and only effective if egpio_present is 1. Once its set, the Island IO is controlled from Chip TLMM. egpio_enable when set to 0 means the GPIO is used as Island Domain IO. To support this we add a new function 'egpio' which can be used to set the egpio_enable to 0, for any other TLMM controlled functions we set the egpio_enable to 1. Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1637041084-3299-1-git-send-email-rnayak@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
158 lines
6.0 KiB
C
158 lines
6.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2013, Sony Mobile Communications AB.
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*/
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#ifndef __PINCTRL_MSM_H__
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#define __PINCTRL_MSM_H__
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struct pinctrl_pin_desc;
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/**
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* struct msm_function - a pinmux function
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* @name: Name of the pinmux function.
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* @groups: List of pingroups for this function.
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* @ngroups: Number of entries in @groups.
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*/
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struct msm_function {
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const char *name;
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const char * const *groups;
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unsigned ngroups;
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};
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/**
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* struct msm_pingroup - Qualcomm pingroup definition
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* @name: Name of the pingroup.
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* @pins: A list of pins assigned to this pingroup.
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* @npins: Number of entries in @pins.
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* @funcs: A list of pinmux functions that can be selected for
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* this group. The index of the selected function is used
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* for programming the function selector.
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* Entries should be indices into the groups list of the
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* struct msm_pinctrl_soc_data.
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* @ctl_reg: Offset of the register holding control bits for this group.
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* @io_reg: Offset of the register holding input/output bits for this group.
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* @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
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* @intr_status_reg: Offset of the register holding the status bits for this group.
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* @intr_target_reg: Offset of the register specifying routing of the interrupts
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* from this group.
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* @mux_bit: Offset in @ctl_reg for the pinmux function selection.
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* @pull_bit: Offset in @ctl_reg for the bias configuration.
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* @drv_bit: Offset in @ctl_reg for the drive strength configuration.
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* @od_bit: Offset in @ctl_reg for controlling open drain.
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* @oe_bit: Offset in @ctl_reg for controlling output enable.
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* @in_bit: Offset in @io_reg for the input bit value.
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* @out_bit: Offset in @io_reg for the output bit value.
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* @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
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* @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
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* status.
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* @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
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* @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
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* this gpio should get routed to the KPSS processor.
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* @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
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* @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
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* @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
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* @intr_detection_width: Number of bits used for specifying interrupt type,
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* Should be 2 for SoCs that can detect both edges in hardware,
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* otherwise 1.
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*/
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struct msm_pingroup {
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const char *name;
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const unsigned *pins;
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unsigned npins;
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unsigned *funcs;
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unsigned nfuncs;
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u32 ctl_reg;
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u32 io_reg;
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u32 intr_cfg_reg;
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u32 intr_status_reg;
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u32 intr_target_reg;
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unsigned int tile:2;
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unsigned mux_bit:5;
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unsigned pull_bit:5;
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unsigned drv_bit:5;
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unsigned od_bit:5;
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unsigned egpio_enable:5;
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unsigned egpio_present:5;
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unsigned oe_bit:5;
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unsigned in_bit:5;
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unsigned out_bit:5;
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unsigned intr_enable_bit:5;
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unsigned intr_status_bit:5;
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unsigned intr_ack_high:1;
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unsigned intr_target_bit:5;
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unsigned intr_target_kpss_val:5;
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unsigned intr_raw_status_bit:5;
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unsigned intr_polarity_bit:5;
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unsigned intr_detection_bit:5;
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unsigned intr_detection_width:5;
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};
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/**
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* struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
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* @gpio: The GPIOs that are wakeup capable
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* @wakeirq: The interrupt at the always-on interrupt controller
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*/
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struct msm_gpio_wakeirq_map {
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unsigned int gpio;
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unsigned int wakeirq;
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};
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/**
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* struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
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* @pins: An array describing all pins the pin controller affects.
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* @npins: The number of entries in @pins.
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* @functions: An array describing all mux functions the SoC supports.
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* @nfunctions: The number of entries in @functions.
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* @groups: An array describing all pin groups the pin SoC supports.
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* @ngroups: The numbmer of entries in @groups.
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* @ngpio: The number of pingroups the driver should expose as GPIOs.
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* @pull_no_keeper: The SoC does not support keeper bias.
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* @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM
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* @nwakeirq_map: The number of entries in @wakeirq_map
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* @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need
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* to be aware that their parent can't handle dual
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* edge interrupts.
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* @gpio_func: Which function number is GPIO (usually 0).
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* @egpio_func: If non-zero then this SoC supports eGPIO. Even though in
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* hardware this is a mux 1-level above the TLMM, we'll treat
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* it as if this is just another mux state of the TLMM. Since
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* it doesn't really map to hardware, we'll allocate a virtual
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* function number for eGPIO and any time we see that function
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* number used we'll treat it as a request to mux away from
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* our TLMM towards another owner.
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*/
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struct msm_pinctrl_soc_data {
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const struct pinctrl_pin_desc *pins;
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unsigned npins;
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const struct msm_function *functions;
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unsigned nfunctions;
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const struct msm_pingroup *groups;
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unsigned ngroups;
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unsigned ngpios;
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bool pull_no_keeper;
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const char *const *tiles;
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unsigned int ntiles;
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const int *reserved_gpios;
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const struct msm_gpio_wakeirq_map *wakeirq_map;
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unsigned int nwakeirq_map;
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bool wakeirq_dual_edge_errata;
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unsigned int gpio_func;
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unsigned int egpio_func;
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};
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extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
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int msm_pinctrl_probe(struct platform_device *pdev,
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const struct msm_pinctrl_soc_data *soc_data);
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int msm_pinctrl_remove(struct platform_device *pdev);
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#endif
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