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Add documentation for the clock buffer select phy property in the am654x and j721e 4 bit IP Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200619125801.9530-2-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
62 lines
2.2 KiB
Plaintext
62 lines
2.2 KiB
Plaintext
Device Tree Bindings for the SDHCI Controllers present on TI's AM654 SOCs
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The bindings follow the mmc[1], clock[2] and interrupt[3] bindings.
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Only deviations are documented here.
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[1] Documentation/devicetree/bindings/mmc/mmc.txt
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[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
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Required Properties:
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- compatible: should be one of:
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"ti,am654-sdhci-5.1": SDHCI on AM654 device.
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"ti,j721e-sdhci-8bit": 8 bit SDHCI on J721E device.
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"ti,j721e-sdhci-4bit": 4 bit SDHCI on J721E device.
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- reg: Must be two entries.
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- The first should be the sdhci register space
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- The second should the subsystem/phy register space
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- clocks: Handles to the clock inputs.
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- clock-names: Tuple including "clk_xin" and "clk_ahb"
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- interrupts: Interrupt specifiers
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Output tap delay for each speed mode:
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- ti,otap-del-sel-legacy
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- ti,otap-del-sel-mmc-hs
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- ti,otap-del-sel-sd-hs
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- ti,otap-del-sel-sdr12
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- ti,otap-del-sel-sdr25
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- ti,otap-del-sel-sdr50
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- ti,otap-del-sel-sdr104
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- ti,otap-del-sel-ddr50
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- ti,otap-del-sel-ddr52
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- ti,otap-del-sel-hs200
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- ti,otap-del-sel-hs400
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These bindings must be provided otherwise the driver will disable the
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corresponding speed mode (i.e. all nodes must provide at least -legacy)
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Optional Properties (Required for ti,am654-sdhci-5.1 and ti,j721e-sdhci-8bit):
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- ti,trm-icp: DLL trim select
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- ti,driver-strength-ohm: driver strength in ohms.
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Valid values are 33, 40, 50, 66 and 100 ohms.
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Optional Properties:
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- ti,strobe-sel: strobe select delay for HS400 speed mode. Default value: 0x0.
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- ti,clkbuf-sel: Clock Delay Buffer Select
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Example:
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sdhci0: sdhci@4f80000 {
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compatible = "ti,am654-sdhci-5.1";
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reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
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power-domains = <&k3_pds 47>;
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clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
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clock-names = "clk_ahb", "clk_xin";
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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sdhci-caps-mask = <0x80000007 0x0>;
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mmc-ddr-1_8v;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-mmc-hs = <0x0>;
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ti,otap-del-sel-ddr52 = <0x5>;
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ti,otap-del-sel-hs200 = <0x5>;
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ti,otap-del-sel-hs400 = <0x0>;
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ti,trm-icp = <0x8>;
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};
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