Wei Wang 3cb9d5464c perf/x86: Fix variable types for LBR registers ... The MSR variable type can be 'unsigned int', which uses less memory than the longer 'unsigned long'. Fix 'struct x86_pmu' for that. The lbr_nr won't be a negative number, so make it 'unsigned int' as well. Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Wei Wang <wei.w.wang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20200613080958.132489-2-like.xu@linux.intel.com		2020-07-02 15:51:45 +02:00
..
amd	Merge branch 'x86/cpu' into perf/core, to resolve conflict	2020-03-25 15:20:44 +01:00
intel	perf/x86/rapl: Move RAPL support to common x86 code	2020-05-28 07:58:55 +02:00
zhaoxin	x86/perf: Add hardware performance events support for Zhaoxin CPU.	2020-04-30 20:14:35 +02:00
core.c	mmap locking API: convert mmap_sem comments	2020-06-09 09:39:14 -07:00
Kconfig	treewide: replace '---help---' in Kconfig files with 'help'	2020-06-14 01:57:21 +09:00
Makefile	perf/x86/rapl: Fix RAPL config variable bug	2020-06-02 11:52:56 +02:00
msr.c	perf/x86/msr: Add Tremont support	2020-02-11 13:17:50 +01:00
perf_event.h	perf/x86: Fix variable types for LBR registers	2020-07-02 15:51:45 +02:00
probe.c	perf/x86/rapl: Make perf_probe_msr() more robust and flexible	2020-05-28 07:58:55 +02:00
probe.h	perf/x86: Add MSR probe interface	2019-06-24 19:28:31 +02:00
rapl.c	perf/x86/rapl: Add AMD Fam17h RAPL support	2020-05-28 07:58:56 +02:00