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fce152a63d
Update all 32bit rockchip devicetree files to use SPDX-License-Identifiers. All files except rk3288-veyron-analog-audio.dtsi (which is GPL 2.0 only) claim to be GPL and X11 while the actual license text is MIT. Use the MIT SPDX tag for them. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Brian Norris <briannorris@chromium.org> Acked-by: Matthias Brugger <mbrugger@suse.com> Acked-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
69 lines
1.3 KiB
Plaintext
69 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/dts-v1/;
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#include "rk322x.dtsi"
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/ {
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model = "Rockchip RK3228 Evaluation board";
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compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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vcc_phy: vcc-phy-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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regulator-name = "vcc_phy";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&emmc {
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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disable-wp;
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non-removable;
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status = "okay";
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};
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&gmac {
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assigned-clocks = <&cru SCLK_MAC_SRC>;
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assigned-clock-rates = <50000000>;
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clock_in_out = "output";
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phy-supply = <&vcc_phy>;
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phy-mode = "rmii";
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phy-handle = <&phy>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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phy: phy@0 {
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compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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clocks = <&cru SCLK_MAC_PHY>;
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resets = <&cru SRST_MACPHY>;
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phy-is-integrated;
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};
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};
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};
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&tsadc {
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status = "okay";
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rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
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rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
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};
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&uart2 {
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status = "okay";
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};
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