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485a40469c
Add the (previously omitted) Ether/PHY pin data to the SK-RZG1E board's device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
76 lines
1.3 KiB
Plaintext
76 lines
1.3 KiB
Plaintext
/*
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* Device Tree Source for the SK-RZG1E board
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*
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* Copyright (C) 2016-2017 Cogent Embedded, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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#include "r8a7745.dtsi"
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/ {
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model = "SK-RZG1E";
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compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
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aliases {
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serial0 = &scif2;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
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stdout-path = "serial0:115200n8";
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x40000000>;
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};
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};
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&extal_clk {
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clock-frequency = <20000000>;
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};
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&pfc {
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scif2_pins: scif2 {
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groups = "scif2_data";
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function = "scif2";
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};
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ether_pins: ether {
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groups = "eth_link", "eth_mdio", "eth_rmii";
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function = "eth";
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};
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phy1_pins: phy1 {
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groups = "intc_irq8";
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function = "intc";
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};
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};
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&scif2 {
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pinctrl-0 = <&scif2_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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ðer {
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pinctrl-0 = <ðer_pins &phy1_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy1>;
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renesas,ether-link-active-low;
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status = "okay";
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phy1: ethernet-phy@1 {
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reg = <1>;
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interrupt-parent = <&irqc>;
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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micrel,led-mode = <1>;
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};
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};
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