mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2025-01-19 20:34:20 +08:00
fef2998203
Convert the Altera Triple Speed Ethernet Controller to phylink. This controller supports MII, GMII and RGMII with its MAC, and SGMII + 1000BaseX through a small embedded PCS. The PCS itself has a register set very similar to what is found in a typical 802.3 ethernet PHY, but this register set memory-mapped instead of lying on an mdio bus. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
13 lines
354 B
Plaintext
13 lines
354 B
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
|
|
config ALTERA_TSE
|
|
tristate "Altera Triple-Speed Ethernet MAC support"
|
|
depends on HAS_DMA
|
|
select PHYLIB
|
|
select PHYLINK
|
|
select PCS_ALTERA_TSE
|
|
help
|
|
This driver supports the Altera Triple-Speed (TSE) Ethernet MAC.
|
|
|
|
To compile this driver as a module, choose M here. The module
|
|
will be called alteratse.
|