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76c567fbba
The Tilera architecture traditionally supports 64KB page sizes to improve TLB utilization and improve performance when the hardware is being used primarily to run a single application. For more generic server scenarios, it can be beneficial to run with 4KB page sizes, so this commit allows that to be specified (by modifying the arch/tile/include/hv/pagesize.h header). As part of this change, we also re-worked the PTE management slightly so that PTE writes all go through a __set_pte() function where we can do some additional validation. The set_pte_order() function was eliminated since the "order" argument wasn't being used. One bug uncovered was in the PCI DMA code, which wasn't properly flushing the specified range. This was benign with 64KB pages, but with 4KB pages we were getting some larger flushes wrong. The per-cpu memory reservation code also needed updating to conform with the newer percpu stuff; before it always chose 64KB, and that was always correct, but with 4KB granularity we now have to pay closer attention and reserve the amount of memory that will be requested when the percpu code starts allocating. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
110 lines
2.6 KiB
C
110 lines
2.6 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_HUGETLB_H
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#define _ASM_TILE_HUGETLB_H
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#include <asm/page.h>
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static inline int is_hugepage_only_range(struct mm_struct *mm,
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unsigned long addr,
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unsigned long len) {
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return 0;
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}
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/*
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* If the arch doesn't supply something else, assume that hugepage
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* size aligned regions are ok without further preparation.
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*/
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static inline int prepare_hugepage_range(struct file *file,
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unsigned long addr, unsigned long len)
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{
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struct hstate *h = hstate_file(file);
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if (len & ~huge_page_mask(h))
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return -EINVAL;
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if (addr & ~huge_page_mask(h))
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return -EINVAL;
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return 0;
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}
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static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
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{
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}
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static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
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unsigned long addr, unsigned long end,
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unsigned long floor,
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unsigned long ceiling)
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{
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free_pgd_range(tlb, addr, end, floor, ceiling);
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}
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static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte)
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{
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set_pte(ptep, pte);
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}
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static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
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unsigned long addr, pte_t *ptep)
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{
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return ptep_get_and_clear(mm, addr, ptep);
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}
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static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep)
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{
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ptep_clear_flush(vma, addr, ptep);
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}
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static inline int huge_pte_none(pte_t pte)
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{
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return pte_none(pte);
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}
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static inline pte_t huge_pte_wrprotect(pte_t pte)
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{
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return pte_wrprotect(pte);
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}
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static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
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unsigned long addr, pte_t *ptep)
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{
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ptep_set_wrprotect(mm, addr, ptep);
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}
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static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep,
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pte_t pte, int dirty)
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{
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return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
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}
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static inline pte_t huge_ptep_get(pte_t *ptep)
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{
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return *ptep;
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}
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static inline int arch_prepare_hugepage(struct page *page)
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{
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return 0;
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}
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static inline void arch_release_hugepage(struct page *page)
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{
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}
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#endif /* _ASM_TILE_HUGETLB_H */
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