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d7c3f8cee8
Omit the segment prefix in the UP case. GS is not used then and we will generate segfaults if cmpxchg16b is used otherwise. Signed-off-by: Christoph Lameter <cl@linux.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
598 lines
20 KiB
C
598 lines
20 KiB
C
#ifndef _ASM_X86_PERCPU_H
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#define _ASM_X86_PERCPU_H
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#ifdef CONFIG_X86_64
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#define __percpu_seg gs
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#define __percpu_mov_op movq
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#else
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#define __percpu_seg fs
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#define __percpu_mov_op movl
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#endif
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#ifdef __ASSEMBLY__
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/*
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* PER_CPU finds an address of a per-cpu variable.
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*
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* Args:
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* var - variable name
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* reg - 32bit register
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*
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* The resulting address is stored in the "reg" argument.
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*
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* Example:
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* PER_CPU(cpu_gdt_descr, %ebx)
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*/
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#ifdef CONFIG_SMP
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#define PER_CPU(var, reg) \
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__percpu_mov_op %__percpu_seg:this_cpu_off, reg; \
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lea var(reg), reg
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#define PER_CPU_VAR(var) %__percpu_seg:var
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#else /* ! SMP */
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#define PER_CPU(var, reg) __percpu_mov_op $var, reg
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#define PER_CPU_VAR(var) var
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#endif /* SMP */
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#ifdef CONFIG_X86_64_SMP
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#define INIT_PER_CPU_VAR(var) init_per_cpu__##var
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#else
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#define INIT_PER_CPU_VAR(var) var
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#endif
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#else /* ...!ASSEMBLY */
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#include <linux/kernel.h>
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#include <linux/stringify.h>
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#ifdef CONFIG_SMP
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#define __percpu_prefix "%%"__stringify(__percpu_seg)":"
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#define __my_cpu_offset percpu_read(this_cpu_off)
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/*
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* Compared to the generic __my_cpu_offset version, the following
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* saves one instruction and avoids clobbering a temp register.
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*/
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#define __this_cpu_ptr(ptr) \
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({ \
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unsigned long tcp_ptr__; \
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__verify_pcpu_ptr(ptr); \
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asm volatile("add " __percpu_arg(1) ", %0" \
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: "=r" (tcp_ptr__) \
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: "m" (this_cpu_off), "0" (ptr)); \
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(typeof(*(ptr)) __kernel __force *)tcp_ptr__; \
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})
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#else
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#define __percpu_prefix ""
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#endif
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#define __percpu_arg(x) __percpu_prefix "%P" #x
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/*
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* Initialized pointers to per-cpu variables needed for the boot
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* processor need to use these macros to get the proper address
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* offset from __per_cpu_load on SMP.
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*
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* There also must be an entry in vmlinux_64.lds.S
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*/
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#define DECLARE_INIT_PER_CPU(var) \
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extern typeof(var) init_per_cpu_var(var)
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#ifdef CONFIG_X86_64_SMP
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#define init_per_cpu_var(var) init_per_cpu__##var
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#else
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#define init_per_cpu_var(var) var
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#endif
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/* For arch-specific code, we can use direct single-insn ops (they
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* don't give an lvalue though). */
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extern void __bad_percpu_size(void);
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#define percpu_to_op(op, var, val) \
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do { \
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typedef typeof(var) pto_T__; \
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if (0) { \
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pto_T__ pto_tmp__; \
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pto_tmp__ = (val); \
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(void)pto_tmp__; \
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} \
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switch (sizeof(var)) { \
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case 1: \
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asm(op "b %1,"__percpu_arg(0) \
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: "+m" (var) \
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: "qi" ((pto_T__)(val))); \
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break; \
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case 2: \
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asm(op "w %1,"__percpu_arg(0) \
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: "+m" (var) \
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: "ri" ((pto_T__)(val))); \
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break; \
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case 4: \
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asm(op "l %1,"__percpu_arg(0) \
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: "+m" (var) \
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: "ri" ((pto_T__)(val))); \
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break; \
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case 8: \
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asm(op "q %1,"__percpu_arg(0) \
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: "+m" (var) \
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: "re" ((pto_T__)(val))); \
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break; \
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default: __bad_percpu_size(); \
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} \
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} while (0)
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/*
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* Generate a percpu add to memory instruction and optimize code
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* if one is added or subtracted.
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*/
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#define percpu_add_op(var, val) \
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do { \
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typedef typeof(var) pao_T__; \
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const int pao_ID__ = (__builtin_constant_p(val) && \
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((val) == 1 || (val) == -1)) ? (val) : 0; \
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if (0) { \
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pao_T__ pao_tmp__; \
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pao_tmp__ = (val); \
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(void)pao_tmp__; \
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} \
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switch (sizeof(var)) { \
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case 1: \
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if (pao_ID__ == 1) \
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asm("incb "__percpu_arg(0) : "+m" (var)); \
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else if (pao_ID__ == -1) \
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asm("decb "__percpu_arg(0) : "+m" (var)); \
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else \
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asm("addb %1, "__percpu_arg(0) \
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: "+m" (var) \
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: "qi" ((pao_T__)(val))); \
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break; \
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case 2: \
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if (pao_ID__ == 1) \
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asm("incw "__percpu_arg(0) : "+m" (var)); \
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else if (pao_ID__ == -1) \
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asm("decw "__percpu_arg(0) : "+m" (var)); \
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else \
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asm("addw %1, "__percpu_arg(0) \
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: "+m" (var) \
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: "ri" ((pao_T__)(val))); \
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break; \
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case 4: \
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if (pao_ID__ == 1) \
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asm("incl "__percpu_arg(0) : "+m" (var)); \
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else if (pao_ID__ == -1) \
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asm("decl "__percpu_arg(0) : "+m" (var)); \
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else \
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asm("addl %1, "__percpu_arg(0) \
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: "+m" (var) \
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: "ri" ((pao_T__)(val))); \
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break; \
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case 8: \
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if (pao_ID__ == 1) \
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asm("incq "__percpu_arg(0) : "+m" (var)); \
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else if (pao_ID__ == -1) \
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asm("decq "__percpu_arg(0) : "+m" (var)); \
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else \
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asm("addq %1, "__percpu_arg(0) \
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: "+m" (var) \
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: "re" ((pao_T__)(val))); \
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break; \
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default: __bad_percpu_size(); \
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} \
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} while (0)
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#define percpu_from_op(op, var, constraint) \
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({ \
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typeof(var) pfo_ret__; \
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switch (sizeof(var)) { \
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case 1: \
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asm(op "b "__percpu_arg(1)",%0" \
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: "=q" (pfo_ret__) \
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: constraint); \
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break; \
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case 2: \
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asm(op "w "__percpu_arg(1)",%0" \
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: "=r" (pfo_ret__) \
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: constraint); \
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break; \
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case 4: \
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asm(op "l "__percpu_arg(1)",%0" \
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: "=r" (pfo_ret__) \
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: constraint); \
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break; \
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case 8: \
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asm(op "q "__percpu_arg(1)",%0" \
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: "=r" (pfo_ret__) \
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: constraint); \
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break; \
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default: __bad_percpu_size(); \
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} \
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pfo_ret__; \
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})
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#define percpu_unary_op(op, var) \
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({ \
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switch (sizeof(var)) { \
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case 1: \
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asm(op "b "__percpu_arg(0) \
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: "+m" (var)); \
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break; \
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case 2: \
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asm(op "w "__percpu_arg(0) \
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: "+m" (var)); \
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break; \
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case 4: \
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asm(op "l "__percpu_arg(0) \
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: "+m" (var)); \
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break; \
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case 8: \
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asm(op "q "__percpu_arg(0) \
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: "+m" (var)); \
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break; \
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default: __bad_percpu_size(); \
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} \
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})
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/*
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* Add return operation
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*/
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#define percpu_add_return_op(var, val) \
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({ \
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typeof(var) paro_ret__ = val; \
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switch (sizeof(var)) { \
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case 1: \
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asm("xaddb %0, "__percpu_arg(1) \
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: "+q" (paro_ret__), "+m" (var) \
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: : "memory"); \
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break; \
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case 2: \
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asm("xaddw %0, "__percpu_arg(1) \
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: "+r" (paro_ret__), "+m" (var) \
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: : "memory"); \
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break; \
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case 4: \
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asm("xaddl %0, "__percpu_arg(1) \
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: "+r" (paro_ret__), "+m" (var) \
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: : "memory"); \
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break; \
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case 8: \
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asm("xaddq %0, "__percpu_arg(1) \
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: "+re" (paro_ret__), "+m" (var) \
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: : "memory"); \
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break; \
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default: __bad_percpu_size(); \
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} \
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paro_ret__ += val; \
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paro_ret__; \
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})
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/*
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* xchg is implemented using cmpxchg without a lock prefix. xchg is
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* expensive due to the implied lock prefix. The processor cannot prefetch
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* cachelines if xchg is used.
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*/
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#define percpu_xchg_op(var, nval) \
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({ \
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typeof(var) pxo_ret__; \
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typeof(var) pxo_new__ = (nval); \
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switch (sizeof(var)) { \
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case 1: \
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asm("\n\tmov "__percpu_arg(1)",%%al" \
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"\n1:\tcmpxchgb %2, "__percpu_arg(1) \
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"\n\tjnz 1b" \
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: "=&a" (pxo_ret__), "+m" (var) \
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: "q" (pxo_new__) \
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: "memory"); \
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break; \
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case 2: \
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asm("\n\tmov "__percpu_arg(1)",%%ax" \
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"\n1:\tcmpxchgw %2, "__percpu_arg(1) \
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"\n\tjnz 1b" \
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: "=&a" (pxo_ret__), "+m" (var) \
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: "r" (pxo_new__) \
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: "memory"); \
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break; \
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case 4: \
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asm("\n\tmov "__percpu_arg(1)",%%eax" \
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"\n1:\tcmpxchgl %2, "__percpu_arg(1) \
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"\n\tjnz 1b" \
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: "=&a" (pxo_ret__), "+m" (var) \
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: "r" (pxo_new__) \
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: "memory"); \
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break; \
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case 8: \
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asm("\n\tmov "__percpu_arg(1)",%%rax" \
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"\n1:\tcmpxchgq %2, "__percpu_arg(1) \
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"\n\tjnz 1b" \
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: "=&a" (pxo_ret__), "+m" (var) \
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: "r" (pxo_new__) \
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: "memory"); \
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break; \
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default: __bad_percpu_size(); \
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} \
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pxo_ret__; \
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})
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/*
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* cmpxchg has no such implied lock semantics as a result it is much
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* more efficient for cpu local operations.
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*/
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#define percpu_cmpxchg_op(var, oval, nval) \
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({ \
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typeof(var) pco_ret__; \
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typeof(var) pco_old__ = (oval); \
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typeof(var) pco_new__ = (nval); \
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switch (sizeof(var)) { \
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case 1: \
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asm("cmpxchgb %2, "__percpu_arg(1) \
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: "=a" (pco_ret__), "+m" (var) \
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: "q" (pco_new__), "0" (pco_old__) \
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: "memory"); \
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break; \
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case 2: \
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asm("cmpxchgw %2, "__percpu_arg(1) \
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: "=a" (pco_ret__), "+m" (var) \
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: "r" (pco_new__), "0" (pco_old__) \
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: "memory"); \
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break; \
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case 4: \
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asm("cmpxchgl %2, "__percpu_arg(1) \
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: "=a" (pco_ret__), "+m" (var) \
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: "r" (pco_new__), "0" (pco_old__) \
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: "memory"); \
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break; \
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case 8: \
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asm("cmpxchgq %2, "__percpu_arg(1) \
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: "=a" (pco_ret__), "+m" (var) \
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: "r" (pco_new__), "0" (pco_old__) \
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: "memory"); \
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break; \
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default: __bad_percpu_size(); \
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} \
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pco_ret__; \
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})
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/*
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* percpu_read() makes gcc load the percpu variable every time it is
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* accessed while percpu_read_stable() allows the value to be cached.
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* percpu_read_stable() is more efficient and can be used if its value
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* is guaranteed to be valid across cpus. The current users include
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* get_current() and get_thread_info() both of which are actually
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* per-thread variables implemented as per-cpu variables and thus
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* stable for the duration of the respective task.
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*/
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#define percpu_read(var) percpu_from_op("mov", var, "m" (var))
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#define percpu_read_stable(var) percpu_from_op("mov", var, "p" (&(var)))
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#define percpu_write(var, val) percpu_to_op("mov", var, val)
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#define percpu_add(var, val) percpu_add_op(var, val)
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#define percpu_sub(var, val) percpu_add_op(var, -(val))
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#define percpu_and(var, val) percpu_to_op("and", var, val)
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#define percpu_or(var, val) percpu_to_op("or", var, val)
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#define percpu_xor(var, val) percpu_to_op("xor", var, val)
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#define percpu_inc(var) percpu_unary_op("inc", var)
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#define __this_cpu_read_1(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
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#define __this_cpu_read_2(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
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#define __this_cpu_read_4(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
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#define __this_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val)
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#define __this_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val)
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#define __this_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val)
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#define __this_cpu_add_1(pcp, val) percpu_add_op((pcp), val)
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#define __this_cpu_add_2(pcp, val) percpu_add_op((pcp), val)
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#define __this_cpu_add_4(pcp, val) percpu_add_op((pcp), val)
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#define __this_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val)
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#define __this_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val)
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#define __this_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val)
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#define __this_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val)
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#define __this_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val)
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#define __this_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val)
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#define __this_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val)
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#define __this_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val)
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#define __this_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val)
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/*
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* Generic fallback operations for __this_cpu_xchg_[1-4] are okay and much
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* faster than an xchg with forced lock semantics.
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*/
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#define __this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval)
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#define __this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
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#define this_cpu_read_1(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
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#define this_cpu_read_2(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
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#define this_cpu_read_4(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
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#define this_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val)
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#define this_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val)
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#define this_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val)
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#define this_cpu_add_1(pcp, val) percpu_add_op((pcp), val)
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#define this_cpu_add_2(pcp, val) percpu_add_op((pcp), val)
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#define this_cpu_add_4(pcp, val) percpu_add_op((pcp), val)
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#define this_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val)
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#define this_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val)
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#define this_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val)
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#define this_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val)
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#define this_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val)
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#define this_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val)
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#define this_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val)
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#define this_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val)
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#define this_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val)
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#define this_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval)
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#define this_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval)
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#define this_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval)
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#define irqsafe_cpu_add_1(pcp, val) percpu_add_op((pcp), val)
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#define irqsafe_cpu_add_2(pcp, val) percpu_add_op((pcp), val)
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#define irqsafe_cpu_add_4(pcp, val) percpu_add_op((pcp), val)
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#define irqsafe_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val)
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#define irqsafe_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val)
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#define irqsafe_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val)
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#define irqsafe_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val)
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#define irqsafe_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val)
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#define irqsafe_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val)
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#define irqsafe_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val)
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#define irqsafe_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val)
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#define irqsafe_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val)
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#define irqsafe_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval)
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#define irqsafe_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval)
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#define irqsafe_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval)
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#ifndef CONFIG_M386
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#define __this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)
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#define __this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
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#define __this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val)
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#define __this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
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#define __this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
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#define __this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
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#define this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)
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#define this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
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#define this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val)
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#define this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
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#define this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
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#define this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
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#define irqsafe_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
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#define irqsafe_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
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#define irqsafe_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
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#endif /* !CONFIG_M386 */
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#ifdef CONFIG_X86_CMPXCHG64
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#define percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) \
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({ \
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char __ret; \
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typeof(o1) __o1 = o1; \
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typeof(o1) __n1 = n1; \
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typeof(o2) __o2 = o2; \
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typeof(o2) __n2 = n2; \
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typeof(o2) __dummy = n2; \
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asm volatile("cmpxchg8b "__percpu_arg(1)"\n\tsetz %0\n\t" \
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: "=a"(__ret), "=m" (pcp1), "=d"(__dummy) \
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: "b"(__n1), "c"(__n2), "a"(__o1), "d"(__o2)); \
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__ret; \
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})
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#define __this_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2)
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#define this_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2)
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#define irqsafe_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2)
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#endif /* CONFIG_X86_CMPXCHG64 */
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/*
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* Per cpu atomic 64 bit operations are only available under 64 bit.
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* 32 bit must fall back to generic operations.
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*/
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#ifdef CONFIG_X86_64
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#define __this_cpu_read_8(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
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#define __this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val)
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#define __this_cpu_add_8(pcp, val) percpu_add_op((pcp), val)
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#define __this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val)
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#define __this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val)
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#define __this_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val)
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#define __this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val)
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#define this_cpu_read_8(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
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#define this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val)
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#define this_cpu_add_8(pcp, val) percpu_add_op((pcp), val)
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#define this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val)
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#define this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val)
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#define this_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val)
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#define this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val)
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#define this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval)
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#define this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
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#define irqsafe_cpu_add_8(pcp, val) percpu_add_op((pcp), val)
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#define irqsafe_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val)
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#define irqsafe_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val)
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#define irqsafe_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val)
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#define irqsafe_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval)
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#define irqsafe_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
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/*
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* Pretty complex macro to generate cmpxchg16 instruction. The instruction
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* is not supported on early AMD64 processors so we must be able to emulate
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* it in software. The address used in the cmpxchg16 instruction must be
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* aligned to a 16 byte boundary.
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*/
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#define percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) \
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({ \
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char __ret; \
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typeof(o1) __o1 = o1; \
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typeof(o1) __n1 = n1; \
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typeof(o2) __o2 = o2; \
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typeof(o2) __n2 = n2; \
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typeof(o2) __dummy; \
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alternative_io("call this_cpu_cmpxchg16b_emu\n\t" P6_NOP4, \
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"cmpxchg16b " __percpu_prefix "(%%rsi)\n\tsetz %0\n\t", \
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X86_FEATURE_CX16, \
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ASM_OUTPUT2("=a"(__ret), "=d"(__dummy)), \
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"S" (&pcp1), "b"(__n1), "c"(__n2), \
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"a"(__o1), "d"(__o2) : "memory"); \
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__ret; \
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})
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#define __this_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2)
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#define this_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2)
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#define irqsafe_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2)
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#endif
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/* This is not atomic against other CPUs -- CPU preemption needs to be off */
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#define x86_test_and_clear_bit_percpu(bit, var) \
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({ \
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int old__; \
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asm volatile("btr %2,"__percpu_arg(1)"\n\tsbbl %0,%0" \
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: "=r" (old__), "+m" (var) \
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: "dIr" (bit)); \
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old__; \
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})
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#include <asm-generic/percpu.h>
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/* We can use this directly for local CPU (faster). */
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DECLARE_PER_CPU(unsigned long, this_cpu_off);
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#endif /* !__ASSEMBLY__ */
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#ifdef CONFIG_SMP
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/*
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|
* Define the "EARLY_PER_CPU" macros. These are used for some per_cpu
|
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* variables that are initialized and accessed before there are per_cpu
|
|
* areas allocated.
|
|
*/
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#define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \
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DEFINE_PER_CPU(_type, _name) = _initvalue; \
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__typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \
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|
{ [0 ... NR_CPUS-1] = _initvalue }; \
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__typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map
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|
|
#define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \
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|
EXPORT_PER_CPU_SYMBOL(_name)
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|
|
|
#define DECLARE_EARLY_PER_CPU(_type, _name) \
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|
DECLARE_PER_CPU(_type, _name); \
|
|
extern __typeof__(_type) *_name##_early_ptr; \
|
|
extern __typeof__(_type) _name##_early_map[]
|
|
|
|
#define early_per_cpu_ptr(_name) (_name##_early_ptr)
|
|
#define early_per_cpu_map(_name, _idx) (_name##_early_map[_idx])
|
|
#define early_per_cpu(_name, _cpu) \
|
|
*(early_per_cpu_ptr(_name) ? \
|
|
&early_per_cpu_ptr(_name)[_cpu] : \
|
|
&per_cpu(_name, _cpu))
|
|
|
|
#else /* !CONFIG_SMP */
|
|
#define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \
|
|
DEFINE_PER_CPU(_type, _name) = _initvalue
|
|
|
|
#define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \
|
|
EXPORT_PER_CPU_SYMBOL(_name)
|
|
|
|
#define DECLARE_EARLY_PER_CPU(_type, _name) \
|
|
DECLARE_PER_CPU(_type, _name)
|
|
|
|
#define early_per_cpu(_name, _cpu) per_cpu(_name, _cpu)
|
|
#define early_per_cpu_ptr(_name) NULL
|
|
/* no early_per_cpu_map() */
|
|
|
|
#endif /* !CONFIG_SMP */
|
|
|
|
#endif /* _ASM_X86_PERCPU_H */
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