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07f08d9cee
Rockchip SoCs use 2 different numbering schemes. Where the gpio- controllers just count 0-31 for their 32 gpios, the underlying iomux controller splits these into 4 separate entities A-D. Device-schematics always use these iomux-values to identify pins, so to make mapping schematics to devicetree easier Andy Yan introduced named constants for the pins but so far we only used them on new additions. Using a sed-script created by Emil Renner Berthing bulk-convert the remaining raw gpio numbers into their descriptive counterparts and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings: /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/<RK_GPIO\([0-9]\) /<\1 /g s/<\([^ ][^ ]* *\)0 /<\1RK_PA0 /g s/<\([^ ][^ ]* *\)1 /<\1RK_PA1 /g s/<\([^ ][^ ]* *\)2 /<\1RK_PA2 /g s/<\([^ ][^ ]* *\)3 /<\1RK_PA3 /g s/<\([^ ][^ ]* *\)4 /<\1RK_PA4 /g s/<\([^ ][^ ]* *\)5 /<\1RK_PA5 /g s/<\([^ ][^ ]* *\)6 /<\1RK_PA6 /g s/<\([^ ][^ ]* *\)7 /<\1RK_PA7 /g s/<\([^ ][^ ]* *\)8 /<\1RK_PB0 /g s/<\([^ ][^ ]* *\)9 /<\1RK_PB1 /g s/<\([^ ][^ ]* *\)10 /<\1RK_PB2 /g s/<\([^ ][^ ]* *\)11 /<\1RK_PB3 /g s/<\([^ ][^ ]* *\)12 /<\1RK_PB4 /g s/<\([^ ][^ ]* *\)13 /<\1RK_PB5 /g s/<\([^ ][^ ]* *\)14 /<\1RK_PB6 /g s/<\([^ ][^ ]* *\)15 /<\1RK_PB7 /g s/<\([^ ][^ ]* *\)16 /<\1RK_PC0 /g s/<\([^ ][^ ]* *\)17 /<\1RK_PC1 /g s/<\([^ ][^ ]* *\)18 /<\1RK_PC2 /g s/<\([^ ][^ ]* *\)19 /<\1RK_PC3 /g s/<\([^ ][^ ]* *\)20 /<\1RK_PC4 /g s/<\([^ ][^ ]* *\)21 /<\1RK_PC5 /g s/<\([^ ][^ ]* *\)22 /<\1RK_PC6 /g s/<\([^ ][^ ]* *\)23 /<\1RK_PC7 /g s/<\([^ ][^ ]* *\)24 /<\1RK_PD0 /g s/<\([^ ][^ ]* *\)25 /<\1RK_PD1 /g s/<\([^ ][^ ]* *\)26 /<\1RK_PD2 /g s/<\([^ ][^ ]* *\)27 /<\1RK_PD3 /g s/<\([^ ][^ ]* *\)28 /<\1RK_PD4 /g s/<\([^ ][^ ]* *\)29 /<\1RK_PD5 /g s/<\([^ ][^ ]* *\)30 /<\1RK_PD6 /g s/<\([^ ][^ ]* *\)31 /<\1RK_PD7 /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)0 /<\1RK_FUNC_GPIO /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)RK_FUNC_\([1-9]\) /<\1\2 /g Suggested-by: Emil Renner Berthing <esmil@mailme.dk> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
90 lines
2.0 KiB
Plaintext
90 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron (and derivatives) fragment for sdmmc cards
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*
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* Copyright 2015 Google, Inc
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*/
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&io_domains {
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sdcard-supply = <&vccio_sd>;
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};
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&pinctrl {
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sdmmc {
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/*
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* We run sdmmc at max speed; bump up drive strength.
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* We also have external pulls, so disable the internal ones.
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*/
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sdmmc_bus4: sdmmc-bus4 {
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rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>,
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<6 RK_PC1 1 &pcfg_pull_none_drv_8ma>,
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<6 RK_PC2 1 &pcfg_pull_none_drv_8ma>,
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<6 RK_PC3 1 &pcfg_pull_none_drv_8ma>;
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};
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sdmmc_clk: sdmmc-clk {
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rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
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};
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sdmmc_cmd: sdmmc-cmd {
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rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>;
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};
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/*
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* Builtin CD line is hooked to ground to prevent JTAG at boot
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* (and also to get the voltage rail correct).
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* Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
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* think there's a card inserted
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*/
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sdmmc_cd_disabled: sdmmc-cd-disabled {
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rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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/* This is where we actually hook up CD */
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sdmmc_cd_gpio: sdmmc-cd-gpio {
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rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&rk808 {
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vcc9-supply = <&vcc_5v>;
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regulators {
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vccio_sd: LDO_REG4 {
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regulator-name = "vccio_sd";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc33_sd: LDO_REG5 {
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regulator-name = "vcc33_sd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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};
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&sdmmc {
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status = "okay";
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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card-detect-delay = <200>;
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cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
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rockchip,default-sample-phase = <90>;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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vmmc-supply = <&vcc33_sd>;
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vqmmc-supply = <&vccio_sd>;
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};
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