mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-24 03:24:55 +08:00
09ad741b7e
The "EDIMM STARTER KIT i.Core 1.5 MIPI Evaluation" is based on the 1.5 version
of the i.Core MX6 cpu module. The 1.5 version differs from the original one for
a few details, including the ethernet PHY interface clock provider.
With this commit, the ethernet interface works properly:
SMSC LAN8710/LAN8720 2188000.ethernet-1:00: attached PHY driver
While before using the 1.5 version, ethernet failed to startup do to un-clocked
PHY interface:
fec 2188000.ethernet eth0: could not attach to PHY
Fixes: 3fe0883577 ("ARM: dts: imx6q: Add Engicam i.CoreM6 1.5 Quad/Dual MIPI starter kit support")
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Jacopo Mondi <jacopo@jmondi.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
34 lines
520 B
Plaintext
34 lines
520 B
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR X11
|
|
/*
|
|
* Copyright (C) 2017 Engicam S.r.l.
|
|
* Copyright (C) 2017 Amarula Solutions B.V.
|
|
* Author: Jagan Teki <jagan@amarulasolutions.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "imx6q.dtsi"
|
|
#include "imx6qdl-icore-1.5.dtsi"
|
|
|
|
/ {
|
|
model = "Engicam i.CoreM6 1.5 Quad/Dual MIPI Starter Kit";
|
|
compatible = "engicam,imx6-icore", "fsl,imx6q";
|
|
};
|
|
|
|
&hdmi {
|
|
ddc-i2c-bus = <&i2c2>;
|
|
status = "okay";
|
|
};
|
|
|
|
&mipi_csi {
|
|
status = "okay";
|
|
};
|
|
|
|
&ov5640 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc3 {
|
|
status = "okay";
|
|
};
|