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ffcea122c4
These were introduced in commit 25ae3a0739 ("[POWERPC] mpc512x: Add
MPC512x PSC support to MPC52xx psc driver") and never used. Moreover
according to the datasheet[1] MEMERROR is bit 25 (0x40) and ORERR is
bit 27 (0x10).
[1] MPC5125RM Rev. 2; 11/2009
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
353 lines
9.9 KiB
C
353 lines
9.9 KiB
C
/*
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* include/asm-ppc/mpc52xx_psc.h
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*
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* Definitions of consts/structs to drive the Freescale MPC52xx OnChip
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* PSCs. Theses are shared between multiple drivers since a PSC can be
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* UART, AC97, IR, I2S, ... So this header is in asm-ppc.
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*
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*
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* Maintainer : Sylvain Munaut <tnt@246tNt.com>
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*
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* Based/Extracted from some header of the 2.4 originally written by
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* Dale Farnsworth <dfarnsworth@mvista.com>
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*
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* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
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* Copyright (C) 2003 MontaVista, Software, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef __ASM_MPC52xx_PSC_H__
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#define __ASM_MPC52xx_PSC_H__
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#include <asm/types.h>
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/* Max number of PSCs */
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#ifdef CONFIG_PPC_MPC512x
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#define MPC52xx_PSC_MAXNUM 12
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#else
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#define MPC52xx_PSC_MAXNUM 6
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#endif
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/* Programmable Serial Controller (PSC) status register bits */
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#define MPC52xx_PSC_SR_UNEX_RX 0x0001
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#define MPC52xx_PSC_SR_DATA_VAL 0x0002
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#define MPC52xx_PSC_SR_DATA_OVR 0x0004
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#define MPC52xx_PSC_SR_CMDSEND 0x0008
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#define MPC52xx_PSC_SR_CDE 0x0080
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#define MPC52xx_PSC_SR_RXRDY 0x0100
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#define MPC52xx_PSC_SR_RXFULL 0x0200
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#define MPC52xx_PSC_SR_TXRDY 0x0400
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#define MPC52xx_PSC_SR_TXEMP 0x0800
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#define MPC52xx_PSC_SR_OE 0x1000
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#define MPC52xx_PSC_SR_PE 0x2000
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#define MPC52xx_PSC_SR_FE 0x4000
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#define MPC52xx_PSC_SR_RB 0x8000
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/* PSC Command values */
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#define MPC52xx_PSC_RX_ENABLE 0x0001
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#define MPC52xx_PSC_RX_DISABLE 0x0002
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#define MPC52xx_PSC_TX_ENABLE 0x0004
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#define MPC52xx_PSC_TX_DISABLE 0x0008
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#define MPC52xx_PSC_SEL_MODE_REG_1 0x0010
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#define MPC52xx_PSC_RST_RX 0x0020
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#define MPC52xx_PSC_RST_TX 0x0030
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#define MPC52xx_PSC_RST_ERR_STAT 0x0040
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#define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050
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#define MPC52xx_PSC_START_BRK 0x0060
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#define MPC52xx_PSC_STOP_BRK 0x0070
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/* PSC TxRx FIFO status bits */
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#define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040
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#define MPC52xx_PSC_RXTX_FIFO_UF 0x0020
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#define MPC52xx_PSC_RXTX_FIFO_OF 0x0010
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#define MPC52xx_PSC_RXTX_FIFO_FR 0x0008
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#define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004
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#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
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#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
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/* PSC interrupt status/mask bits */
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#define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001
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#define MPC52xx_PSC_IMR_DATA_VALID 0x0002
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#define MPC52xx_PSC_IMR_DATA_OVR 0x0004
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#define MPC52xx_PSC_IMR_CMD_SEND 0x0008
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#define MPC52xx_PSC_IMR_ERROR 0x0040
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#define MPC52xx_PSC_IMR_DEOF 0x0080
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#define MPC52xx_PSC_IMR_TXRDY 0x0100
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#define MPC52xx_PSC_IMR_RXRDY 0x0200
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#define MPC52xx_PSC_IMR_DB 0x0400
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#define MPC52xx_PSC_IMR_TXEMP 0x0800
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#define MPC52xx_PSC_IMR_ORERR 0x1000
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#define MPC52xx_PSC_IMR_IPC 0x8000
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/* PSC input port change bits */
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#define MPC52xx_PSC_CTS 0x01
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#define MPC52xx_PSC_DCD 0x02
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#define MPC52xx_PSC_D_CTS 0x10
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#define MPC52xx_PSC_D_DCD 0x20
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/* PSC acr bits */
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#define MPC52xx_PSC_IEC_CTS 0x01
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#define MPC52xx_PSC_IEC_DCD 0x02
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/* PSC output port bits */
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#define MPC52xx_PSC_OP_RTS 0x01
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#define MPC52xx_PSC_OP_RES 0x02
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/* PSC mode fields */
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#define MPC52xx_PSC_MODE_5_BITS 0x00
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#define MPC52xx_PSC_MODE_6_BITS 0x01
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#define MPC52xx_PSC_MODE_7_BITS 0x02
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#define MPC52xx_PSC_MODE_8_BITS 0x03
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#define MPC52xx_PSC_MODE_BITS_MASK 0x03
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#define MPC52xx_PSC_MODE_PAREVEN 0x00
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#define MPC52xx_PSC_MODE_PARODD 0x04
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#define MPC52xx_PSC_MODE_PARFORCE 0x08
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#define MPC52xx_PSC_MODE_PARNONE 0x10
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#define MPC52xx_PSC_MODE_ERR 0x20
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#define MPC52xx_PSC_MODE_FFULL 0x40
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#define MPC52xx_PSC_MODE_RXRTS 0x80
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#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00
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#define MPC52xx_PSC_MODE_ONE_STOP 0x07
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#define MPC52xx_PSC_MODE_TWO_STOP 0x0f
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#define MPC52xx_PSC_MODE_TXCTS 0x10
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#define MPC52xx_PSC_RFNUM_MASK 0x01ff
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#define MPC52xx_PSC_SICR_DTS1 (1 << 29)
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#define MPC52xx_PSC_SICR_SHDR (1 << 28)
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#define MPC52xx_PSC_SICR_SIM_MASK (0xf << 24)
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#define MPC52xx_PSC_SICR_SIM_UART (0x0 << 24)
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#define MPC52xx_PSC_SICR_SIM_UART_DCD (0x8 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_8 (0x1 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_16 (0x2 << 24)
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#define MPC52xx_PSC_SICR_SIM_AC97 (0x3 << 24)
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#define MPC52xx_PSC_SICR_SIM_SIR (0x8 << 24)
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#define MPC52xx_PSC_SICR_SIM_SIR_DCD (0xc << 24)
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#define MPC52xx_PSC_SICR_SIM_MIR (0x5 << 24)
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#define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24)
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#define MPC52xx_PSC_SICR_ACRB (0x8 << 24)
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#define MPC52xx_PSC_SICR_AWR (1 << 30)
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#define MPC52xx_PSC_SICR_GENCLK (1 << 23)
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#define MPC52xx_PSC_SICR_I2S (1 << 22)
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#define MPC52xx_PSC_SICR_CLKPOL (1 << 21)
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#define MPC52xx_PSC_SICR_SYNCPOL (1 << 20)
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#define MPC52xx_PSC_SICR_CELLSLAVE (1 << 19)
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#define MPC52xx_PSC_SICR_CELL2XCLK (1 << 18)
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#define MPC52xx_PSC_SICR_ESAI (1 << 17)
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#define MPC52xx_PSC_SICR_ENAC97 (1 << 16)
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#define MPC52xx_PSC_SICR_SPI (1 << 15)
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#define MPC52xx_PSC_SICR_MSTR (1 << 14)
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#define MPC52xx_PSC_SICR_CPOL (1 << 13)
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#define MPC52xx_PSC_SICR_CPHA (1 << 12)
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#define MPC52xx_PSC_SICR_USEEOF (1 << 11)
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#define MPC52xx_PSC_SICR_DISABLEEOF (1 << 10)
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/* Structure of the hardware registers */
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struct mpc52xx_psc {
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union {
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u8 mode; /* PSC + 0x00 */
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u8 mr2;
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};
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u8 reserved0[3];
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union { /* PSC + 0x04 */
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u16 status;
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u16 clock_select;
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} sr_csr;
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#define mpc52xx_psc_status sr_csr.status
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#define mpc52xx_psc_clock_select sr_csr.clock_select
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u16 reserved1;
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u8 command; /* PSC + 0x08 */
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u8 reserved2[3];
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union { /* PSC + 0x0c */
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u8 buffer_8;
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u16 buffer_16;
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u32 buffer_32;
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} buffer;
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#define mpc52xx_psc_buffer_8 buffer.buffer_8
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#define mpc52xx_psc_buffer_16 buffer.buffer_16
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#define mpc52xx_psc_buffer_32 buffer.buffer_32
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union { /* PSC + 0x10 */
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u8 ipcr;
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u8 acr;
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} ipcr_acr;
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#define mpc52xx_psc_ipcr ipcr_acr.ipcr
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#define mpc52xx_psc_acr ipcr_acr.acr
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u8 reserved3[3];
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union { /* PSC + 0x14 */
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u16 isr;
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u16 imr;
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} isr_imr;
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#define mpc52xx_psc_isr isr_imr.isr
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#define mpc52xx_psc_imr isr_imr.imr
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u16 reserved4;
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u8 ctur; /* PSC + 0x18 */
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u8 reserved5[3];
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u8 ctlr; /* PSC + 0x1c */
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u8 reserved6[3];
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/* BitClkDiv field of CCR is byte swapped in
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* the hardware for mpc5200/b compatibility */
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u32 ccr; /* PSC + 0x20 */
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u32 ac97_slots; /* PSC + 0x24 */
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u32 ac97_cmd; /* PSC + 0x28 */
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u32 ac97_data; /* PSC + 0x2c */
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u8 ivr; /* PSC + 0x30 */
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u8 reserved8[3];
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u8 ip; /* PSC + 0x34 */
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u8 reserved9[3];
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u8 op1; /* PSC + 0x38 */
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u8 reserved10[3];
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u8 op0; /* PSC + 0x3c */
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u8 reserved11[3];
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u32 sicr; /* PSC + 0x40 */
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u8 ircr1; /* PSC + 0x44 */
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u8 reserved13[3];
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u8 ircr2; /* PSC + 0x44 */
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u8 reserved14[3];
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u8 irsdr; /* PSC + 0x4c */
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u8 reserved15[3];
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u8 irmdr; /* PSC + 0x50 */
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u8 reserved16[3];
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u8 irfdr; /* PSC + 0x54 */
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u8 reserved17[3];
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};
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struct mpc52xx_psc_fifo {
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u16 rfnum; /* PSC + 0x58 */
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u16 reserved18;
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u16 tfnum; /* PSC + 0x5c */
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u16 reserved19;
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u32 rfdata; /* PSC + 0x60 */
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u16 rfstat; /* PSC + 0x64 */
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u16 reserved20;
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u8 rfcntl; /* PSC + 0x68 */
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u8 reserved21[5];
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u16 rfalarm; /* PSC + 0x6e */
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u16 reserved22;
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u16 rfrptr; /* PSC + 0x72 */
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u16 reserved23;
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u16 rfwptr; /* PSC + 0x76 */
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u16 reserved24;
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u16 rflrfptr; /* PSC + 0x7a */
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u16 reserved25;
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u16 rflwfptr; /* PSC + 0x7e */
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u32 tfdata; /* PSC + 0x80 */
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u16 tfstat; /* PSC + 0x84 */
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u16 reserved26;
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u8 tfcntl; /* PSC + 0x88 */
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u8 reserved27[5];
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u16 tfalarm; /* PSC + 0x8e */
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u16 reserved28;
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u16 tfrptr; /* PSC + 0x92 */
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u16 reserved29;
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u16 tfwptr; /* PSC + 0x96 */
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u16 reserved30;
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u16 tflrfptr; /* PSC + 0x9a */
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u16 reserved31;
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u16 tflwfptr; /* PSC + 0x9e */
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};
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#define MPC512x_PSC_FIFO_EOF 0x100
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#define MPC512x_PSC_FIFO_RESET_SLICE 0x80
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#define MPC512x_PSC_FIFO_ENABLE_SLICE 0x01
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#define MPC512x_PSC_FIFO_ENABLE_DMA 0x04
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#define MPC512x_PSC_FIFO_EMPTY 0x1
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#define MPC512x_PSC_FIFO_FULL 0x2
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#define MPC512x_PSC_FIFO_ALARM 0x4
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#define MPC512x_PSC_FIFO_URERR 0x8
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struct mpc512x_psc_fifo {
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u32 reserved1[10];
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u32 txcmd; /* PSC + 0x80 */
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u32 txalarm; /* PSC + 0x84 */
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u32 txsr; /* PSC + 0x88 */
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u32 txisr; /* PSC + 0x8c */
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u32 tximr; /* PSC + 0x90 */
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u32 txcnt; /* PSC + 0x94 */
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u32 txptr; /* PSC + 0x98 */
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u32 txsz; /* PSC + 0x9c */
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u32 reserved2[7];
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union {
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u8 txdata_8;
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u16 txdata_16;
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u32 txdata_32;
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} txdata; /* PSC + 0xbc */
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#define txdata_8 txdata.txdata_8
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#define txdata_16 txdata.txdata_16
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#define txdata_32 txdata.txdata_32
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u32 rxcmd; /* PSC + 0xc0 */
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u32 rxalarm; /* PSC + 0xc4 */
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u32 rxsr; /* PSC + 0xc8 */
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u32 rxisr; /* PSC + 0xcc */
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u32 rximr; /* PSC + 0xd0 */
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u32 rxcnt; /* PSC + 0xd4 */
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u32 rxptr; /* PSC + 0xd8 */
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u32 rxsz; /* PSC + 0xdc */
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u32 reserved3[7];
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union {
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u8 rxdata_8;
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u16 rxdata_16;
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u32 rxdata_32;
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} rxdata; /* PSC + 0xfc */
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#define rxdata_8 rxdata.rxdata_8
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#define rxdata_16 rxdata.rxdata_16
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#define rxdata_32 rxdata.rxdata_32
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};
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struct mpc5125_psc {
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u8 mr1; /* PSC + 0x00 */
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u8 reserved0[3];
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u8 mr2; /* PSC + 0x04 */
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u8 reserved1[3];
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struct {
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u16 status; /* PSC + 0x08 */
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u8 reserved2[2];
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u8 clock_select; /* PSC + 0x0c */
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u8 reserved3[3];
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} sr_csr;
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u8 command; /* PSC + 0x10 */
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u8 reserved4[3];
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union { /* PSC + 0x14 */
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u8 buffer_8;
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u16 buffer_16;
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u32 buffer_32;
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} buffer;
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struct {
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u8 ipcr; /* PSC + 0x18 */
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u8 reserved5[3];
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u8 acr; /* PSC + 0x1c */
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u8 reserved6[3];
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} ipcr_acr;
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struct {
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u16 isr; /* PSC + 0x20 */
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u8 reserved7[2];
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u16 imr; /* PSC + 0x24 */
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u8 reserved8[2];
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} isr_imr;
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u8 ctur; /* PSC + 0x28 */
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u8 reserved9[3];
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u8 ctlr; /* PSC + 0x2c */
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u8 reserved10[3];
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u32 ccr; /* PSC + 0x30 */
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u32 ac97slots; /* PSC + 0x34 */
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u32 ac97cmd; /* PSC + 0x38 */
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u32 ac97data; /* PSC + 0x3c */
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u8 reserved11[4];
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u8 ip; /* PSC + 0x44 */
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u8 reserved12[3];
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u8 op1; /* PSC + 0x48 */
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u8 reserved13[3];
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u8 op0; /* PSC + 0x4c */
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u8 reserved14[3];
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u32 sicr; /* PSC + 0x50 */
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u8 reserved15[4]; /* make eq. sizeof(mpc52xx_psc) */
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};
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#endif /* __ASM_MPC52xx_PSC_H__ */
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