Dan Williams 399d34ebc2 cxl/core: Refactor CXL register lookup for bridge reuse ... While CXL Memory Device endpoints locate the CXL MMIO registers in a PCI BAR, CXL root bridges have their MMIO base address described by platform firmware. Refactor the existing register lookup into a generic facility for endpoints and bridges to share. Reviewed-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/162096972534.1865304.3218686216153688039.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2021-05-14 16:13:19 -07:00
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core.c	cxl/core: Refactor CXL register lookup for bridge reuse	2021-05-14 16:13:19 -07:00
cxl.h	cxl/core: Refactor CXL register lookup for bridge reuse	2021-05-14 16:13:19 -07:00
Kconfig	cxl/mem: Add a "RAW" send command	2021-02-16 20:36:38 -08:00
Makefile	cxl/core: Rename bus.c to core.c	2021-05-14 16:13:19 -07:00
mem.c	cxl/core: Refactor CXL register lookup for bridge reuse	2021-05-14 16:13:19 -07:00
mem.h	cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices	2021-05-14 16:13:19 -07:00
pci.h