linux/include/soc
Thierry Reding 393d66fd2c memory: tegra: Implement SID override programming
Instead of programming all SID overrides during early boot, perform the
operation on-demand after the SMMU translations have been set up for a
device. This reuses data from device tree to match memory clients for a
device and programs the SID specified in device tree, which corresponds
to the SID used for the SMMU context banks for the device.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20210603164632.1000458-2-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-03 21:50:43 +02:00
..
arc include/: replace HTTP links with HTTPS ones 2020-08-12 10:57:59 -07:00
at91 ARM: at91: pm: Move prototypes to mutually included header 2021-03-26 18:20:49 +01:00
bcm2835 firmware: raspberrypi: Introduce devm_rpi_firmware_get() 2021-03-22 17:59:51 +01:00
canaan clk: Add RISC-V Canaan Kendryte K210 clock driver 2021-02-22 17:51:04 -08:00
fsl Revert "soc: fsl: qe: introduce qe_io{read,write}* wrappers" 2021-04-06 15:40:48 -05:00
imx ARM: imx: move cpu definitions into a header 2020-05-20 23:03:47 +08:00
mediatek IOMMU Updates for Linux v5.12 2021-02-22 10:31:29 -08:00
mscc net: mscc: ocelot: support PTP Sync one-step timestamping 2021-04-27 14:10:15 -07:00
qcom soc: qcom: rpmh: Remove serialization of TCS commands 2021-01-07 10:59:46 -06:00
rockchip treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 2019-06-05 17:36:37 +02:00
sa1100 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
sifive riscv: move sifive_l2_cache.h to include/soc 2020-01-12 10:12:44 -08:00
tegra memory: tegra: Implement SID override programming 2021-06-03 21:50:43 +02:00