mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
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f77d26a9fc
to fixup conflicts in arch/x86/kernel/cpu/mce/core.c so MCE specific follow up patches can be applied without creating a horrible merge conflict afterwards.
649 lines
17 KiB
C
649 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
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* processor hardware monitoring
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*
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* Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
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* Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
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*
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* Implementation notes:
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* - CCD register address information as well as the calculation to
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* convert raw register values is from https://github.com/ocerman/zenpower.
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* The information is not confirmed from chip datasheets, but experiments
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* suggest that it provides reasonable temperature values.
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* - Register addresses to read chip voltage and current are also from
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* https://github.com/ocerman/zenpower, and not confirmed from chip
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* datasheets. Current calibration is board specific and not typically
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* shared by board vendors. For this reason, current values are
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* normalized to report 1A/LSB for core current and and 0.25A/LSB for SoC
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* current. Reported values can be adjusted using the sensors configuration
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* file.
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*/
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#include <linux/bitops.h>
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#include <linux/debugfs.h>
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#include <linux/err.h>
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#include <linux/hwmon.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <asm/amd_nb.h>
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#include <asm/processor.h>
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MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
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MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
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MODULE_LICENSE("GPL");
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static bool force;
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module_param(force, bool, 0444);
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MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
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/* Provide lock for writing to NB_SMU_IND_ADDR */
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static DEFINE_MUTEX(nb_smu_ind_mutex);
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#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
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#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
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#endif
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/* CPUID function 0x80000001, ebx */
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#define CPUID_PKGTYPE_MASK GENMASK(31, 28)
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#define CPUID_PKGTYPE_F 0x00000000
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#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
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/* DRAM controller (PCI function 2) */
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#define REG_DCT0_CONFIG_HIGH 0x094
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#define DDR3_MODE BIT(8)
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/* miscellaneous (PCI function 3) */
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#define REG_HARDWARE_THERMAL_CONTROL 0x64
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#define HTC_ENABLE BIT(0)
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#define REG_REPORTED_TEMPERATURE 0xa4
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#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
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#define NB_CAP_HTC BIT(10)
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/*
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* For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
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* and REG_REPORTED_TEMPERATURE have been moved to
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* D0F0xBC_xD820_0C64 [Hardware Temperature Control]
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* D0F0xBC_xD820_0CA4 [Reported Temperature Control]
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*/
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#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
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#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
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/* F17h M01h Access througn SMN */
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#define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800
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#define F17H_M70H_CCD_TEMP(x) (0x00059954 + ((x) * 4))
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#define F17H_M70H_CCD_TEMP_VALID BIT(11)
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#define F17H_M70H_CCD_TEMP_MASK GENMASK(10, 0)
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#define F17H_M01H_SVI 0x0005A000
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#define F17H_M01H_SVI_TEL_PLANE0 (F17H_M01H_SVI + 0xc)
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#define F17H_M01H_SVI_TEL_PLANE1 (F17H_M01H_SVI + 0x10)
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#define CUR_TEMP_SHIFT 21
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#define CUR_TEMP_RANGE_SEL_MASK BIT(19)
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#define CFACTOR_ICORE 1000000 /* 1A / LSB */
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#define CFACTOR_ISOC 250000 /* 0.25A / LSB */
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struct k10temp_data {
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struct pci_dev *pdev;
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void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
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void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
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int temp_offset;
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u32 temp_adjust_mask;
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u32 show_temp;
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u32 svi_addr[2];
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bool is_zen;
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bool show_current;
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int cfactor[2];
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};
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#define TCTL_BIT 0
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#define TDIE_BIT 1
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#define TCCD_BIT(x) ((x) + 2)
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#define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel))
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#define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT)
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struct tctl_offset {
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u8 model;
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char const *id;
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int offset;
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};
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static const struct tctl_offset tctl_offset_table[] = {
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{ 0x17, "AMD Ryzen 5 1600X", 20000 },
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{ 0x17, "AMD Ryzen 7 1700X", 20000 },
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{ 0x17, "AMD Ryzen 7 1800X", 20000 },
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{ 0x17, "AMD Ryzen 7 2700X", 10000 },
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{ 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
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{ 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
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};
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static bool is_threadripper(void)
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{
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return strstr(boot_cpu_data.x86_model_id, "Threadripper");
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}
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static bool is_epyc(void)
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{
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return strstr(boot_cpu_data.x86_model_id, "EPYC");
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}
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static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
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{
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pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
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}
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static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
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{
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pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
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}
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static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
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unsigned int base, int offset, u32 *val)
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{
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mutex_lock(&nb_smu_ind_mutex);
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pci_bus_write_config_dword(pdev->bus, devfn,
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base, offset);
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pci_bus_read_config_dword(pdev->bus, devfn,
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base + 4, val);
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mutex_unlock(&nb_smu_ind_mutex);
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}
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static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
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{
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amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
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F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
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}
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static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
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{
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amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
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F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
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}
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static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
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{
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amd_smn_read(amd_pci_dev_to_node_id(pdev),
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F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
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}
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static long get_raw_temp(struct k10temp_data *data)
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{
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u32 regval;
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long temp;
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data->read_tempreg(data->pdev, ®val);
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temp = (regval >> CUR_TEMP_SHIFT) * 125;
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if (regval & data->temp_adjust_mask)
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temp -= 49000;
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return temp;
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}
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static const char *k10temp_temp_label[] = {
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"Tctl",
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"Tdie",
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"Tccd1",
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"Tccd2",
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"Tccd3",
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"Tccd4",
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"Tccd5",
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"Tccd6",
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"Tccd7",
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"Tccd8",
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};
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static const char *k10temp_in_label[] = {
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"Vcore",
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"Vsoc",
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};
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static const char *k10temp_curr_label[] = {
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"Icore",
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"Isoc",
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};
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static int k10temp_read_labels(struct device *dev,
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enum hwmon_sensor_types type,
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u32 attr, int channel, const char **str)
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{
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switch (type) {
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case hwmon_temp:
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*str = k10temp_temp_label[channel];
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break;
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case hwmon_in:
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*str = k10temp_in_label[channel];
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break;
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case hwmon_curr:
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*str = k10temp_curr_label[channel];
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int k10temp_read_curr(struct device *dev, u32 attr, int channel,
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long *val)
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{
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struct k10temp_data *data = dev_get_drvdata(dev);
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u32 regval;
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switch (attr) {
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case hwmon_curr_input:
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amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
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data->svi_addr[channel], ®val);
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*val = DIV_ROUND_CLOSEST(data->cfactor[channel] *
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(regval & 0xff),
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1000);
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int k10temp_read_in(struct device *dev, u32 attr, int channel, long *val)
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{
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struct k10temp_data *data = dev_get_drvdata(dev);
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u32 regval;
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switch (attr) {
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case hwmon_in_input:
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amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
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data->svi_addr[channel], ®val);
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regval = (regval >> 16) & 0xff;
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*val = DIV_ROUND_CLOSEST(155000 - regval * 625, 100);
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
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long *val)
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{
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struct k10temp_data *data = dev_get_drvdata(dev);
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u32 regval;
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switch (attr) {
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case hwmon_temp_input:
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switch (channel) {
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case 0: /* Tctl */
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*val = get_raw_temp(data);
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if (*val < 0)
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*val = 0;
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break;
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case 1: /* Tdie */
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*val = get_raw_temp(data) - data->temp_offset;
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if (*val < 0)
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*val = 0;
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break;
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case 2 ... 9: /* Tccd{1-8} */
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amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
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F17H_M70H_CCD_TEMP(channel - 2), ®val);
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*val = (regval & F17H_M70H_CCD_TEMP_MASK) * 125 - 49000;
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break;
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default:
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return -EOPNOTSUPP;
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}
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break;
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case hwmon_temp_max:
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*val = 70 * 1000;
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break;
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case hwmon_temp_crit:
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data->read_htcreg(data->pdev, ®val);
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*val = ((regval >> 16) & 0x7f) * 500 + 52000;
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break;
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case hwmon_temp_crit_hyst:
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data->read_htcreg(data->pdev, ®val);
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*val = (((regval >> 16) & 0x7f)
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- ((regval >> 24) & 0xf)) * 500 + 52000;
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
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u32 attr, int channel, long *val)
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{
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switch (type) {
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case hwmon_temp:
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return k10temp_read_temp(dev, attr, channel, val);
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case hwmon_in:
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return k10temp_read_in(dev, attr, channel, val);
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case hwmon_curr:
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return k10temp_read_curr(dev, attr, channel, val);
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default:
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return -EOPNOTSUPP;
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}
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}
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static umode_t k10temp_is_visible(const void *_data,
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enum hwmon_sensor_types type,
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u32 attr, int channel)
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{
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const struct k10temp_data *data = _data;
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struct pci_dev *pdev = data->pdev;
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u32 reg;
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switch (type) {
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case hwmon_temp:
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switch (attr) {
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case hwmon_temp_input:
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if (!HAVE_TEMP(data, channel))
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return 0;
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break;
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case hwmon_temp_max:
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if (channel || data->is_zen)
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return 0;
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break;
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case hwmon_temp_crit:
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case hwmon_temp_crit_hyst:
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if (channel || !data->read_htcreg)
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return 0;
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pci_read_config_dword(pdev,
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REG_NORTHBRIDGE_CAPABILITIES,
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®);
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if (!(reg & NB_CAP_HTC))
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return 0;
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data->read_htcreg(data->pdev, ®);
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if (!(reg & HTC_ENABLE))
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return 0;
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break;
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case hwmon_temp_label:
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/* Show temperature labels only on Zen CPUs */
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if (!data->is_zen || !HAVE_TEMP(data, channel))
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return 0;
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break;
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default:
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return 0;
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}
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break;
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case hwmon_in:
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case hwmon_curr:
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if (!data->show_current)
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return 0;
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break;
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default:
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return 0;
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}
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return 0444;
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}
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static bool has_erratum_319(struct pci_dev *pdev)
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{
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u32 pkg_type, reg_dram_cfg;
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if (boot_cpu_data.x86 != 0x10)
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return false;
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/*
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* Erratum 319: The thermal sensor of Socket F/AM2+ processors
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* may be unreliable.
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*/
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pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
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if (pkg_type == CPUID_PKGTYPE_F)
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return true;
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if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
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return false;
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/* DDR3 memory implies socket AM3, which is good */
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pci_bus_read_config_dword(pdev->bus,
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PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
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REG_DCT0_CONFIG_HIGH, ®_dram_cfg);
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if (reg_dram_cfg & DDR3_MODE)
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return false;
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/*
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* Unfortunately it is possible to run a socket AM3 CPU with DDR2
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* memory. We blacklist all the cores which do exist in socket AM2+
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* format. It still isn't perfect, as RB-C2 cores exist in both AM2+
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* and AM3 formats, but that's the best we can do.
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*/
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return boot_cpu_data.x86_model < 4 ||
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(boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
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}
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#ifdef CONFIG_DEBUG_FS
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static void k10temp_smn_regs_show(struct seq_file *s, struct pci_dev *pdev,
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u32 addr, int count)
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{
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u32 reg;
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int i;
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for (i = 0; i < count; i++) {
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if (!(i & 3))
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seq_printf(s, "0x%06x: ", addr + i * 4);
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amd_smn_read(amd_pci_dev_to_node_id(pdev), addr + i * 4, ®);
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seq_printf(s, "%08x ", reg);
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if ((i & 3) == 3)
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seq_puts(s, "\n");
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}
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}
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static int svi_show(struct seq_file *s, void *unused)
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{
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struct k10temp_data *data = s->private;
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k10temp_smn_regs_show(s, data->pdev, F17H_M01H_SVI, 32);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(svi);
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static int thm_show(struct seq_file *s, void *unused)
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{
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struct k10temp_data *data = s->private;
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k10temp_smn_regs_show(s, data->pdev,
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F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, 256);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(thm);
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static void k10temp_debugfs_cleanup(void *ddir)
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{
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debugfs_remove_recursive(ddir);
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}
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static void k10temp_init_debugfs(struct k10temp_data *data)
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{
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struct dentry *debugfs;
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char name[32];
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/* Only show debugfs data for Family 17h/18h CPUs */
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if (!data->is_zen)
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return;
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scnprintf(name, sizeof(name), "k10temp-%s", pci_name(data->pdev));
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debugfs = debugfs_create_dir(name, NULL);
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if (debugfs) {
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debugfs_create_file("svi", 0444, debugfs, data, &svi_fops);
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debugfs_create_file("thm", 0444, debugfs, data, &thm_fops);
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devm_add_action_or_reset(&data->pdev->dev,
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k10temp_debugfs_cleanup, debugfs);
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}
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}
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#else
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static void k10temp_init_debugfs(struct k10temp_data *data)
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{
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}
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#endif
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static const struct hwmon_channel_info *k10temp_info[] = {
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HWMON_CHANNEL_INFO(temp,
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HWMON_T_INPUT | HWMON_T_MAX |
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HWMON_T_CRIT | HWMON_T_CRIT_HYST |
|
|
HWMON_T_LABEL,
|
|
HWMON_T_INPUT | HWMON_T_LABEL,
|
|
HWMON_T_INPUT | HWMON_T_LABEL,
|
|
HWMON_T_INPUT | HWMON_T_LABEL,
|
|
HWMON_T_INPUT | HWMON_T_LABEL,
|
|
HWMON_T_INPUT | HWMON_T_LABEL,
|
|
HWMON_T_INPUT | HWMON_T_LABEL,
|
|
HWMON_T_INPUT | HWMON_T_LABEL,
|
|
HWMON_T_INPUT | HWMON_T_LABEL,
|
|
HWMON_T_INPUT | HWMON_T_LABEL),
|
|
HWMON_CHANNEL_INFO(in,
|
|
HWMON_I_INPUT | HWMON_I_LABEL,
|
|
HWMON_I_INPUT | HWMON_I_LABEL),
|
|
HWMON_CHANNEL_INFO(curr,
|
|
HWMON_C_INPUT | HWMON_C_LABEL,
|
|
HWMON_C_INPUT | HWMON_C_LABEL),
|
|
NULL
|
|
};
|
|
|
|
static const struct hwmon_ops k10temp_hwmon_ops = {
|
|
.is_visible = k10temp_is_visible,
|
|
.read = k10temp_read,
|
|
.read_string = k10temp_read_labels,
|
|
};
|
|
|
|
static const struct hwmon_chip_info k10temp_chip_info = {
|
|
.ops = &k10temp_hwmon_ops,
|
|
.info = k10temp_info,
|
|
};
|
|
|
|
static void k10temp_get_ccd_support(struct pci_dev *pdev,
|
|
struct k10temp_data *data, int limit)
|
|
{
|
|
u32 regval;
|
|
int i;
|
|
|
|
for (i = 0; i < limit; i++) {
|
|
amd_smn_read(amd_pci_dev_to_node_id(pdev),
|
|
F17H_M70H_CCD_TEMP(i), ®val);
|
|
if (regval & F17H_M70H_CCD_TEMP_VALID)
|
|
data->show_temp |= BIT(TCCD_BIT(i));
|
|
}
|
|
}
|
|
|
|
static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|
{
|
|
int unreliable = has_erratum_319(pdev);
|
|
struct device *dev = &pdev->dev;
|
|
struct k10temp_data *data;
|
|
struct device *hwmon_dev;
|
|
int i;
|
|
|
|
if (unreliable) {
|
|
if (!force) {
|
|
dev_err(dev,
|
|
"unreliable CPU thermal sensor; monitoring disabled\n");
|
|
return -ENODEV;
|
|
}
|
|
dev_warn(dev,
|
|
"unreliable CPU thermal sensor; check erratum 319\n");
|
|
}
|
|
|
|
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
data->pdev = pdev;
|
|
data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */
|
|
|
|
if (boot_cpu_data.x86 == 0x15 &&
|
|
((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
|
|
(boot_cpu_data.x86_model & 0xf0) == 0x70)) {
|
|
data->read_htcreg = read_htcreg_nb_f15;
|
|
data->read_tempreg = read_tempreg_nb_f15;
|
|
} else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
|
|
data->temp_adjust_mask = CUR_TEMP_RANGE_SEL_MASK;
|
|
data->read_tempreg = read_tempreg_nb_f17;
|
|
data->show_temp |= BIT(TDIE_BIT); /* show Tdie */
|
|
data->is_zen = true;
|
|
|
|
switch (boot_cpu_data.x86_model) {
|
|
case 0x1: /* Zen */
|
|
case 0x8: /* Zen+ */
|
|
case 0x11: /* Zen APU */
|
|
case 0x18: /* Zen+ APU */
|
|
data->show_current = !is_threadripper() && !is_epyc();
|
|
data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE0;
|
|
data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE1;
|
|
data->cfactor[0] = CFACTOR_ICORE;
|
|
data->cfactor[1] = CFACTOR_ISOC;
|
|
k10temp_get_ccd_support(pdev, data, 4);
|
|
break;
|
|
case 0x31: /* Zen2 Threadripper */
|
|
case 0x71: /* Zen2 */
|
|
data->show_current = !is_threadripper() && !is_epyc();
|
|
data->cfactor[0] = CFACTOR_ICORE;
|
|
data->cfactor[1] = CFACTOR_ISOC;
|
|
data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE1;
|
|
data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE0;
|
|
k10temp_get_ccd_support(pdev, data, 8);
|
|
break;
|
|
}
|
|
} else {
|
|
data->read_htcreg = read_htcreg_pci;
|
|
data->read_tempreg = read_tempreg_pci;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
|
|
const struct tctl_offset *entry = &tctl_offset_table[i];
|
|
|
|
if (boot_cpu_data.x86 == entry->model &&
|
|
strstr(boot_cpu_data.x86_model_id, entry->id)) {
|
|
data->temp_offset = entry->offset;
|
|
break;
|
|
}
|
|
}
|
|
|
|
hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
|
|
&k10temp_chip_info,
|
|
NULL);
|
|
if (IS_ERR(hwmon_dev))
|
|
return PTR_ERR(hwmon_dev);
|
|
|
|
k10temp_init_debugfs(data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pci_device_id k10temp_id_table[] = {
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
|
|
{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, k10temp_id_table);
|
|
|
|
static struct pci_driver k10temp_driver = {
|
|
.name = "k10temp",
|
|
.id_table = k10temp_id_table,
|
|
.probe = k10temp_probe,
|
|
};
|
|
|
|
module_pci_driver(k10temp_driver);
|