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8107c859a3
Referencing parents with clk_hw pointers is more efficient and removes the dependency on global clock names. clk_parent_data is needed when some parent clocks are provided from another driver. Add macros for declaring muxes that take advantage of these. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119043545.4010-5-samuel@sholland.org
151 lines
3.9 KiB
C
151 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _CCU_MUX_H_
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#define _CCU_MUX_H_
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#include <linux/clk-provider.h>
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#include "ccu_common.h"
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struct ccu_mux_fixed_prediv {
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u8 index;
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u16 div;
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};
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struct ccu_mux_var_prediv {
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u8 index;
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u8 shift;
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u8 width;
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};
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struct ccu_mux_internal {
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u8 shift;
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u8 width;
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const u8 *table;
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const struct ccu_mux_fixed_prediv *fixed_predivs;
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u8 n_predivs;
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const struct ccu_mux_var_prediv *var_predivs;
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u8 n_var_predivs;
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};
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#define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \
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{ \
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.shift = _shift, \
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.width = _width, \
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.table = _table, \
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}
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#define _SUNXI_CCU_MUX(_shift, _width) \
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_SUNXI_CCU_MUX_TABLE(_shift, _width, NULL)
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struct ccu_mux {
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u32 enable;
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struct ccu_mux_internal mux;
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struct ccu_common common;
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};
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#define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \
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_reg, _shift, _width, _gate, \
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_flags) \
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struct ccu_mux _struct = { \
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.enable = _gate, \
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.mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
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.common = { \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS(_name, \
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_parents, \
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&ccu_mux_ops, \
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_flags), \
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} \
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}
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#define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \
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_shift, _width, _gate, _flags) \
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SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
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_reg, _shift, _width, _gate, \
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_flags)
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#define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \
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_flags) \
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SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
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_reg, _shift, _width, 0, _flags)
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#define SUNXI_CCU_MUX_DATA_WITH_GATE(_struct, _name, _parents, _reg, \
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_shift, _width, _gate, _flags) \
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struct ccu_mux _struct = { \
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.enable = _gate, \
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.mux = _SUNXI_CCU_MUX(_shift, _width), \
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.common = { \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
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_parents, \
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&ccu_mux_ops, \
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_flags), \
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} \
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}
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#define SUNXI_CCU_MUX_DATA(_struct, _name, _parents, _reg, \
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_shift, _width, _flags) \
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SUNXI_CCU_MUX_DATA_WITH_GATE(_struct, _name, _parents, _reg, \
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_shift, _width, 0, _flags)
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#define SUNXI_CCU_MUX_HW_WITH_GATE(_struct, _name, _parents, _reg, \
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_shift, _width, _gate, _flags) \
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struct ccu_mux _struct = { \
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.enable = _gate, \
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.mux = _SUNXI_CCU_MUX(_shift, _width), \
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.common = { \
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.reg = _reg, \
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.hw.init = CLK_HW_INIT_PARENTS_HW(_name, \
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_parents, \
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&ccu_mux_ops, \
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_flags), \
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} \
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}
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static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw)
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{
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struct ccu_common *common = hw_to_ccu_common(hw);
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return container_of(common, struct ccu_mux, common);
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}
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extern const struct clk_ops ccu_mux_ops;
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unsigned long ccu_mux_helper_apply_prediv(struct ccu_common *common,
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struct ccu_mux_internal *cm,
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int parent_index,
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unsigned long parent_rate);
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int ccu_mux_helper_determine_rate(struct ccu_common *common,
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struct ccu_mux_internal *cm,
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struct clk_rate_request *req,
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unsigned long (*round)(struct ccu_mux_internal *,
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struct clk_hw *,
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unsigned long *,
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unsigned long,
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void *),
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void *data);
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u8 ccu_mux_helper_get_parent(struct ccu_common *common,
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struct ccu_mux_internal *cm);
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int ccu_mux_helper_set_parent(struct ccu_common *common,
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struct ccu_mux_internal *cm,
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u8 index);
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struct ccu_mux_nb {
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struct notifier_block clk_nb;
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struct ccu_common *common;
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struct ccu_mux_internal *cm;
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u32 delay_us; /* How many us to wait after reparenting */
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u8 bypass_index; /* Which parent to temporarily use */
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u8 original_index; /* This is set by the notifier callback */
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};
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#define to_ccu_mux_nb(_nb) container_of(_nb, struct ccu_mux_nb, clk_nb)
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int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb);
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#endif /* _CCU_MUX_H_ */
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