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df558854cf
Add constants and callback functions for the dwmac on rk3368 socs. As can be seen, the base structure is the same, only registers and the bits in them moved slightly. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: David S. Miller <davem@davemloft.net>
69 lines
2.6 KiB
Plaintext
69 lines
2.6 KiB
Plaintext
Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
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The device node has following properties.
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Required properties:
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- compatible: Can be one of "rockchip,rk3288-gmac", "rockchip,rk3368-gmac"
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- reg: addresses and length of the register sets for the device.
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- interrupts: Should contain the GMAC interrupts.
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- interrupt-names: Should contain the interrupt names "macirq".
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- rockchip,grf: phandle to the syscon grf used to control speed and mode.
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- clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.
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<&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC
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<&cru SCLK_MAC_RX>: clock gate for RX
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<&cru SCLK_MAC_TX>: clock gate for TX
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<&cru SCLK_MACREF>: clock gate for RMII referce clock
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<&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
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<&cru ACLK_GMAC>: AXI clock gate for GMAC
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<&cru PCLK_GMAC>: APB clock gate for GMAC
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- clock-names: One name for each entry in the clocks property.
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- phy-mode: See ethernet.txt file in the same directory.
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- pinctrl-names: Names corresponding to the numbered pinctrl states.
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- pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
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- clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
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is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
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PHY provides the reference clock(50MHz), "output" means GMAC provides the
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reference clock.
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- snps,reset-gpio gpio number for phy reset.
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- snps,reset-active-low boolean flag to indicate if phy reset is active low.
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- assigned-clocks: main clock, should be <&cru SCLK_MAC>;
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- assigned-clock-parents = parent of main clock.
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can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
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Optional properties:
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- tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
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- rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
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- phy-supply: phandle to a regulator if the PHY needs one
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Example:
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gmac: ethernet@ff290000 {
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compatible = "rockchip,rk3288-gmac";
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reg = <0xff290000 0x10000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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rockchip,grf = <&grf>;
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clocks = <&cru SCLK_MAC>,
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<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
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<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
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<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
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clock-names = "stmmaceth",
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"mac_clk_rx", "mac_clk_tx",
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"clk_mac_ref", "clk_mac_refout",
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"aclk_mac", "pclk_mac";
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phy-mode = "rgmii";
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins /*&rmii_pins*/>;
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clock_in_out = "input";
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snps,reset-gpio = <&gpio4 7 0>;
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snps,reset-active-low;
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assigned-clocks = <&cru SCLK_MAC>;
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assigned-clock-parents = <&ext_gmac>;
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tx_delay = <0x30>;
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rx_delay = <0x10>;
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status = "ok";
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};
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