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b43ab901d6
Sodaville has GPIO controller behind the PCI bus. To my suprissed it is not the same as on PXA. The interrupt & gpio chip can be referenced from the device tree like from any other driver. Unfortunately the driver which uses the gpio interrupt has to use irq_of_parse_and_map() instead of platform_get_irq(). The problem is that the platform device (which is created from the device tree) is most likely created before the interrupt chip is registered and therefore irq_of_parse_and_map() fails. In theory the driver works as module. In reality most of the irq functions are not exported to modules and it is possible that _this_ module is unloaded while the provided irqs are still in use. Signed-off-by: Hans J. Koch <hjk@linutronix.de> [torbenh@linutronix.de: make it work after the irq namespace cleanup, add some device tree entries.] Signed-off-by: Torben Hohn <torbenh@linutronix.de> [bigeasy@linutronix.de: convert to generic irq & gpio chip] Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> [grant.likely@secretlab.ca: depend on x86 to avoid irq_domain breakage] Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
434 lines
8.9 KiB
Plaintext
434 lines
8.9 KiB
Plaintext
/*
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* CE4100 on Falcon Falls
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*
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* (c) Copyright 2010 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; version 2 of the License.
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*/
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/dts-v1/;
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/ {
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model = "intel,falconfalls";
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compatible = "intel,falconfalls";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,ce4100";
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reg = <0>;
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lapic = <&lapic0>;
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};
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};
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soc@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "intel,ce4100-cp";
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ranges;
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ioapic1: interrupt-controller@fec00000 {
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#interrupt-cells = <2>;
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compatible = "intel,ce4100-ioapic";
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interrupt-controller;
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reg = <0xfec00000 0x1000>;
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};
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timer@fed00000 {
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compatible = "intel,ce4100-hpet";
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reg = <0xfed00000 0x200>;
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};
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lapic0: interrupt-controller@fee00000 {
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compatible = "intel,ce4100-lapic";
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reg = <0xfee00000 0x1000>;
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};
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pci@3fc {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,ce4100-pci", "pci";
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device_type = "pci";
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bus-range = <0 0>;
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ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
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0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
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0x0000000 0 0x0 0x0 0 0x100>;
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/* Secondary IO-APIC */
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ioapic2: interrupt-controller@0,1 {
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#interrupt-cells = <2>;
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compatible = "intel,ce4100-ioapic";
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interrupt-controller;
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reg = <0x100 0x0 0x0 0x0 0x0>;
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assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>;
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};
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pci@1,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,ce4100-pci", "pci";
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device_type = "pci";
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bus-range = <1 1>;
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reg = <0x0800 0x0 0x0 0x0 0x0>;
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ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>;
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interrupt-parent = <&ioapic2>;
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display@2,0 {
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compatible = "pci8086,2e5b.2",
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"pci8086,2e5b",
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"pciclass038000",
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"pciclass0380";
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reg = <0x11000 0x0 0x0 0x0 0x0>;
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interrupts = <0 1>;
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};
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multimedia@3,0 {
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compatible = "pci8086,2e5c.2",
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"pci8086,2e5c",
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"pciclass048000",
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"pciclass0480";
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reg = <0x11800 0x0 0x0 0x0 0x0>;
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interrupts = <2 1>;
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};
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multimedia@4,0 {
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compatible = "pci8086,2e5d.2",
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"pci8086,2e5d",
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"pciclass048000",
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"pciclass0480";
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reg = <0x12000 0x0 0x0 0x0 0x0>;
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interrupts = <4 1>;
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};
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multimedia@4,1 {
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compatible = "pci8086,2e5e.2",
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"pci8086,2e5e",
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"pciclass048000",
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"pciclass0480";
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reg = <0x12100 0x0 0x0 0x0 0x0>;
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interrupts = <5 1>;
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};
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sound@6,0 {
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compatible = "pci8086,2e5f.2",
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"pci8086,2e5f",
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"pciclass040100",
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"pciclass0401";
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reg = <0x13000 0x0 0x0 0x0 0x0>;
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interrupts = <6 1>;
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};
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sound@6,1 {
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compatible = "pci8086,2e5f.2",
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"pci8086,2e5f",
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"pciclass040100",
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"pciclass0401";
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reg = <0x13100 0x0 0x0 0x0 0x0>;
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interrupts = <7 1>;
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};
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sound@6,2 {
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compatible = "pci8086,2e60.2",
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"pci8086,2e60",
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"pciclass040100",
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"pciclass0401";
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reg = <0x13200 0x0 0x0 0x0 0x0>;
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interrupts = <8 1>;
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};
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display@8,0 {
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compatible = "pci8086,2e61.2",
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"pci8086,2e61",
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"pciclass038000",
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"pciclass0380";
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reg = <0x14000 0x0 0x0 0x0 0x0>;
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interrupts = <9 1>;
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};
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display@8,1 {
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compatible = "pci8086,2e62.2",
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"pci8086,2e62",
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"pciclass038000",
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"pciclass0380";
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reg = <0x14100 0x0 0x0 0x0 0x0>;
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interrupts = <10 1>;
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};
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multimedia@8,2 {
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compatible = "pci8086,2e63.2",
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"pci8086,2e63",
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"pciclass048000",
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"pciclass0480";
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reg = <0x14200 0x0 0x0 0x0 0x0>;
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interrupts = <11 1>;
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};
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entertainment-encryption@9,0 {
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compatible = "pci8086,2e64.2",
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"pci8086,2e64",
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"pciclass101000",
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"pciclass1010";
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reg = <0x14800 0x0 0x0 0x0 0x0>;
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interrupts = <12 1>;
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};
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localbus@a,0 {
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compatible = "pci8086,2e65.2",
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"pci8086,2e65",
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"pciclassff0000",
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"pciclassff00";
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reg = <0x15000 0x0 0x0 0x0 0x0>;
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};
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serial@b,0 {
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compatible = "pci8086,2e66.2",
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"pci8086,2e66",
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"pciclass070003",
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"pciclass0700";
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reg = <0x15800 0x0 0x0 0x0 0x0>;
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interrupts = <14 1>;
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};
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pcigpio: gpio@b,1 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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compatible = "pci8086,2e67.2",
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"pci8086,2e67",
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"pciclassff0000",
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"pciclassff00";
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reg = <0x15900 0x0 0x0 0x0 0x0>;
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interrupts = <15 1>;
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interrupt-controller;
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gpio-controller;
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intel,muxctl = <0>;
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};
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i2c-controller@b,2 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "pci8086,2e68.2",
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"pci8086,2e68",
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"pciclass,ff0000",
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"pciclass,ff00";
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reg = <0x15a00 0x0 0x0 0x0 0x0>;
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interrupts = <16 1>;
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ranges = <0 0 0x02000000 0 0xdffe0500 0x100
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1 0 0x02000000 0 0xdffe0600 0x100
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2 0 0x02000000 0 0xdffe0700 0x100>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ce4100-i2c-controller";
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reg = <0 0 0x100>;
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ce4100-i2c-controller";
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reg = <1 0 0x100>;
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gpio@26 {
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#gpio-cells = <2>;
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compatible = "ti,pcf8575";
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reg = <0x26>;
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gpio-controller;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ce4100-i2c-controller";
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reg = <2 0 0x100>;
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gpio@26 {
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#gpio-cells = <2>;
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compatible = "ti,pcf8575";
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reg = <0x26>;
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gpio-controller;
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};
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};
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};
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smard-card@b,3 {
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compatible = "pci8086,2e69.2",
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"pci8086,2e69",
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"pciclass070500",
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"pciclass0705";
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reg = <0x15b00 0x0 0x0 0x0 0x0>;
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interrupts = <15 1>;
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};
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spi-controller@b,4 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible =
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"pci8086,2e6a.2",
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"pci8086,2e6a",
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"pciclass,ff0000",
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"pciclass,ff00";
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reg = <0x15c00 0x0 0x0 0x0 0x0>;
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interrupts = <15 1>;
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dac@0 {
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compatible = "ti,pcm1755";
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reg = <0>;
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spi-max-frequency = <115200>;
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};
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dac@1 {
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compatible = "ti,pcm1609a";
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reg = <1>;
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spi-max-frequency = <115200>;
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};
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eeprom@2 {
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compatible = "atmel,at93c46";
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reg = <2>;
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spi-max-frequency = <115200>;
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};
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};
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multimedia@b,7 {
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compatible = "pci8086,2e6d.2",
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"pci8086,2e6d",
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"pciclassff0000",
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"pciclassff00";
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reg = <0x15f00 0x0 0x0 0x0 0x0>;
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};
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ethernet@c,0 {
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compatible = "pci8086,2e6e.2",
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"pci8086,2e6e",
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"pciclass020000",
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"pciclass0200";
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reg = <0x16000 0x0 0x0 0x0 0x0>;
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interrupts = <21 1>;
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};
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clock@c,1 {
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compatible = "pci8086,2e6f.2",
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"pci8086,2e6f",
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"pciclassff0000",
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"pciclassff00";
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reg = <0x16100 0x0 0x0 0x0 0x0>;
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interrupts = <3 1>;
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};
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usb@d,0 {
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compatible = "pci8086,2e70.2",
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"pci8086,2e70",
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"pciclass0c0320",
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"pciclass0c03";
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reg = <0x16800 0x0 0x0 0x0 0x0>;
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interrupts = <22 1>;
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};
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usb@d,1 {
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compatible = "pci8086,2e70.2",
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"pci8086,2e70",
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"pciclass0c0320",
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"pciclass0c03";
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reg = <0x16900 0x0 0x0 0x0 0x0>;
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interrupts = <22 1>;
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};
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sata@e,0 {
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compatible = "pci8086,2e71.0",
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"pci8086,2e71",
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"pciclass010601",
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"pciclass0106";
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reg = <0x17000 0x0 0x0 0x0 0x0>;
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interrupts = <23 1>;
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};
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flash@f,0 {
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compatible = "pci8086,701.1",
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"pci8086,701",
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"pciclass050100",
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"pciclass0501";
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reg = <0x17800 0x0 0x0 0x0 0x0>;
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interrupts = <13 1>;
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};
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entertainment-encryption@10,0 {
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compatible = "pci8086,702.1",
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"pci8086,702",
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"pciclass101000",
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"pciclass1010";
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reg = <0x18000 0x0 0x0 0x0 0x0>;
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};
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co-processor@11,0 {
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compatible = "pci8086,703.1",
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"pci8086,703",
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"pciclass0b4000",
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"pciclass0b40";
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reg = <0x18800 0x0 0x0 0x0 0x0>;
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interrupts = <1 1>;
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};
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multimedia@12,0 {
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compatible = "pci8086,704.0",
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"pci8086,704",
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"pciclass048000",
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"pciclass0480";
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reg = <0x19000 0x0 0x0 0x0 0x0>;
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};
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};
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isa@1f,0 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "isa";
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reg = <0xf800 0x0 0x0 0x0 0x0>;
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ranges = <1 0 0 0 0 0x100>;
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rtc@70 {
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compatible = "intel,ce4100-rtc", "motorola,mc146818";
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interrupts = <8 3>;
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interrupt-parent = <&ioapic1>;
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ctrl-reg = <2>;
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freq-reg = <0x26>;
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reg = <1 0x70 2>;
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};
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};
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};
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};
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};
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