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f52b69f86e
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Merge tag 'sh-for-linus' of git://github.com/pmundt/linux-sh
Pull SuperH updates from Paul Mundt.
* tag 'sh-for-linus' of git://github.com/pmundt/linux-sh: (25 commits)
sh: Support I/O space swapping where needed.
sh: use set_current_blocked() and block_sigmask()
sh: no need to reset handler if SA_ONESHOT
sh: intc: Fix up section mismatch for intc_ack_data
sh: select ARCH_DISCARD_MEMBLOCK.
sh: Consolidate duplicate _32/_64 unistd definitions.
sh: ecovec: switch SDHI controllers to card polling
sh: Avoid exporting unimplemented syscalls.
sh: add platform_device for RSPI in setup-sh7757
SH: pci-sh7780: enable big-endian operation.
serial: sh-sci: fix a race of DMA submit_tx on transfer
sh: dma: Collect up CHCR of SH7763, SH7764, SH7780 and SH7785
sh: dma: Collect up CHCR of SH7723 and SH7730
sh/next: Fix build fail by asm/system.h in asm/bitops.h
arch/sh/drivers/dma/{dma-g2,dmabrg}.c: ensure arguments to request_irq and free_irq are compatible
sh: cpufreq: Wire up scaling_available_freqs support.
sh: cpufreq: notify about rate rounding fallback.
sh: cpufreq: Support CPU clock frequency table.
sh: cpufreq: struct device lookup from CPU topology.
sh: cpufreq: percpu struct clk accounting.
...
307 lines
6.8 KiB
C
307 lines
6.8 KiB
C
/*
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* Shared interrupt handling code for IPR and INTC2 types of IRQs.
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*
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* Copyright (C) 2007, 2008 Magnus Damm
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* Copyright (C) 2009, 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/spinlock.h>
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#include "internals.h"
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static unsigned long ack_handle[INTC_NR_IRQS];
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static intc_enum __init intc_grp_id(struct intc_desc *desc,
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intc_enum enum_id)
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{
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struct intc_group *g = desc->hw.groups;
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unsigned int i, j;
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for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
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g = desc->hw.groups + i;
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for (j = 0; g->enum_ids[j]; j++) {
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if (g->enum_ids[j] != enum_id)
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continue;
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return g->enum_id;
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}
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}
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return 0;
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}
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static unsigned int __init _intc_mask_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id,
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unsigned int *reg_idx,
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unsigned int *fld_idx)
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{
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struct intc_mask_reg *mr = desc->hw.mask_regs;
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unsigned int fn, mode;
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unsigned long reg_e, reg_d;
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while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
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mr = desc->hw.mask_regs + *reg_idx;
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for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) {
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if (mr->enum_ids[*fld_idx] != enum_id)
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continue;
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if (mr->set_reg && mr->clr_reg) {
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fn = REG_FN_WRITE_BASE;
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mode = MODE_DUAL_REG;
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reg_e = mr->clr_reg;
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reg_d = mr->set_reg;
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} else {
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fn = REG_FN_MODIFY_BASE;
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if (mr->set_reg) {
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mode = MODE_ENABLE_REG;
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reg_e = mr->set_reg;
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reg_d = mr->set_reg;
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} else {
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mode = MODE_MASK_REG;
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reg_e = mr->clr_reg;
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reg_d = mr->clr_reg;
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}
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}
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fn += (mr->reg_width >> 3) - 1;
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return _INTC_MK(fn, mode,
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intc_get_reg(d, reg_e),
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intc_get_reg(d, reg_d),
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1,
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(mr->reg_width - 1) - *fld_idx);
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}
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*fld_idx = 0;
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(*reg_idx)++;
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}
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return 0;
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}
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unsigned int __init
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intc_get_mask_handle(struct intc_desc *desc, struct intc_desc_int *d,
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intc_enum enum_id, int do_grps)
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{
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unsigned int i = 0;
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unsigned int j = 0;
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unsigned int ret;
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ret = _intc_mask_data(desc, d, enum_id, &i, &j);
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if (ret)
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return ret;
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if (do_grps)
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return intc_get_mask_handle(desc, d, intc_grp_id(desc, enum_id), 0);
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return 0;
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}
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static unsigned int __init _intc_prio_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id,
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unsigned int *reg_idx,
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unsigned int *fld_idx)
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{
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struct intc_prio_reg *pr = desc->hw.prio_regs;
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unsigned int fn, n, mode, bit;
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unsigned long reg_e, reg_d;
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while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
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pr = desc->hw.prio_regs + *reg_idx;
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for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) {
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if (pr->enum_ids[*fld_idx] != enum_id)
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continue;
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if (pr->set_reg && pr->clr_reg) {
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fn = REG_FN_WRITE_BASE;
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mode = MODE_PCLR_REG;
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reg_e = pr->set_reg;
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reg_d = pr->clr_reg;
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} else {
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fn = REG_FN_MODIFY_BASE;
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mode = MODE_PRIO_REG;
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if (!pr->set_reg)
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BUG();
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reg_e = pr->set_reg;
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reg_d = pr->set_reg;
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}
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fn += (pr->reg_width >> 3) - 1;
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n = *fld_idx + 1;
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BUG_ON(n * pr->field_width > pr->reg_width);
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bit = pr->reg_width - (n * pr->field_width);
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return _INTC_MK(fn, mode,
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intc_get_reg(d, reg_e),
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intc_get_reg(d, reg_d),
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pr->field_width, bit);
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}
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*fld_idx = 0;
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(*reg_idx)++;
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}
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return 0;
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}
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unsigned int __init
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intc_get_prio_handle(struct intc_desc *desc, struct intc_desc_int *d,
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intc_enum enum_id, int do_grps)
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{
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unsigned int i = 0;
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unsigned int j = 0;
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unsigned int ret;
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ret = _intc_prio_data(desc, d, enum_id, &i, &j);
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if (ret)
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return ret;
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if (do_grps)
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return intc_get_prio_handle(desc, d, intc_grp_id(desc, enum_id), 0);
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return 0;
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}
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static unsigned int intc_ack_data(struct intc_desc *desc,
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struct intc_desc_int *d, intc_enum enum_id)
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{
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struct intc_mask_reg *mr = desc->hw.ack_regs;
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unsigned int i, j, fn, mode;
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unsigned long reg_e, reg_d;
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for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
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mr = desc->hw.ack_regs + i;
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for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
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if (mr->enum_ids[j] != enum_id)
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continue;
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fn = REG_FN_MODIFY_BASE;
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mode = MODE_ENABLE_REG;
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reg_e = mr->set_reg;
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reg_d = mr->set_reg;
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fn += (mr->reg_width >> 3) - 1;
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return _INTC_MK(fn, mode,
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intc_get_reg(d, reg_e),
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intc_get_reg(d, reg_d),
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1,
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(mr->reg_width - 1) - j);
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}
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}
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return 0;
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}
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static void intc_enable_disable(struct intc_desc_int *d,
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unsigned long handle, int do_enable)
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{
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unsigned long addr;
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unsigned int cpu;
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unsigned long (*fn)(unsigned long, unsigned long,
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unsigned long (*)(unsigned long, unsigned long,
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unsigned long),
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unsigned int);
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if (do_enable) {
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for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
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addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
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fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
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fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
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}
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} else {
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for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
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addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
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fn = intc_disable_fns[_INTC_MODE(handle)];
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fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
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}
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}
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}
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void __init intc_enable_disable_enum(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id, int enable)
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{
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unsigned int i, j, data;
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/* go through and enable/disable all mask bits */
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i = j = 0;
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do {
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data = _intc_mask_data(desc, d, enum_id, &i, &j);
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if (data)
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intc_enable_disable(d, data, enable);
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j++;
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} while (data);
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/* go through and enable/disable all priority fields */
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i = j = 0;
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do {
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data = _intc_prio_data(desc, d, enum_id, &i, &j);
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if (data)
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intc_enable_disable(d, data, enable);
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j++;
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} while (data);
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}
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unsigned int __init
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intc_get_sense_handle(struct intc_desc *desc, struct intc_desc_int *d,
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intc_enum enum_id)
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{
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struct intc_sense_reg *sr = desc->hw.sense_regs;
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unsigned int i, j, fn, bit;
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for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
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sr = desc->hw.sense_regs + i;
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for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
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if (sr->enum_ids[j] != enum_id)
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continue;
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fn = REG_FN_MODIFY_BASE;
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fn += (sr->reg_width >> 3) - 1;
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BUG_ON((j + 1) * sr->field_width > sr->reg_width);
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bit = sr->reg_width - ((j + 1) * sr->field_width);
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return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
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0, sr->field_width, bit);
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}
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}
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return 0;
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}
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void intc_set_ack_handle(unsigned int irq, struct intc_desc *desc,
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struct intc_desc_int *d, intc_enum id)
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{
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unsigned long flags;
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/*
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* Nothing to do for this IRQ.
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*/
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if (!desc->hw.ack_regs)
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return;
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raw_spin_lock_irqsave(&intc_big_lock, flags);
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ack_handle[irq] = intc_ack_data(desc, d, id);
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raw_spin_unlock_irqrestore(&intc_big_lock, flags);
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}
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unsigned long intc_get_ack_handle(unsigned int irq)
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{
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return ack_handle[irq];
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}
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