mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-14 15:54:15 +08:00
945a51517c
after review of all intel drivers, found several instances where drivers had the incorrect pattern of: memory mapped write(); delay(); which should always be: memory mapped write(); write flush(); /* aka memory mapped read */ delay(); explanation: The reason for including the flush is that writes can be held (posted) in PCI/PCIe bridges, but the read always has to complete synchronously and therefore has to flush all pending writes to a device. If a write is held and followed by a delay, the delay means nothing because the write may not have reached hardware (maybe even not until the next read) Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> |
||
|---|---|---|
| .. | ||
| ixgb_ee.c | ||
| ixgb_ee.h | ||
| ixgb_ethtool.c | ||
| ixgb_hw.c | ||
| ixgb_hw.h | ||
| ixgb_ids.h | ||
| ixgb_main.c | ||
| ixgb_osdep.h | ||
| ixgb_param.c | ||
| ixgb.h | ||
| Makefile | ||