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34440ed697
GM20B requires an extra clock compared to GK20A. Add that information into the platform data and acquire and enable this clock if necessary. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
97 lines
2.9 KiB
C
97 lines
2.9 KiB
C
/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "nouveau_platform.h"
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static int nouveau_platform_probe(struct platform_device *pdev)
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{
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const struct nvkm_device_tegra_func *func;
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struct nvkm_device *device = NULL;
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struct drm_device *drm;
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int ret;
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func = of_device_get_match_data(&pdev->dev);
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drm = nouveau_platform_device_create(func, pdev, &device);
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if (IS_ERR(drm))
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return PTR_ERR(drm);
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ret = drm_dev_register(drm, 0);
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if (ret < 0) {
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drm_dev_unref(drm);
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return ret;
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}
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return 0;
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}
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static int nouveau_platform_remove(struct platform_device *pdev)
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{
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struct drm_device *dev = platform_get_drvdata(pdev);
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nouveau_drm_device_remove(dev);
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return 0;
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}
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#if IS_ENABLED(CONFIG_OF)
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static const struct nvkm_device_tegra_func gk20a_platform_data = {
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.iommu_bit = 34,
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};
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static const struct nvkm_device_tegra_func gm20b_platform_data = {
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.iommu_bit = 34,
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.require_ref_clk = true,
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};
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static const struct of_device_id nouveau_platform_match[] = {
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{
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.compatible = "nvidia,gk20a",
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.data = &gk20a_platform_data,
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},
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{
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.compatible = "nvidia,gm20b",
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.data = &gm20b_platform_data,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, nouveau_platform_match);
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#endif
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struct platform_driver nouveau_platform_driver = {
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.driver = {
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.name = "nouveau",
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.of_match_table = of_match_ptr(nouveau_platform_match),
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},
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.probe = nouveau_platform_probe,
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.remove = nouveau_platform_remove,
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};
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) || IS_ENABLED(CONFIG_ARCH_TEGRA_132_SOC)
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MODULE_FIRMWARE("nvidia/gk20a/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gk20a/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gk20a/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gk20a/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gk20a/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gk20a/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gk20a/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/gk20a/sw_nonctx.bin");
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#endif
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