Palmer Dabbelt 982a7eb97b Documentation: RISC-V: uabi: Only scalar misaligned loads are supported ... We're stuck supporting scalar misaligned loads in userspace because they were part of the ISA at the time we froze the uABI. That wasn't the case for vector misaligned accesses, so depending on them unconditionally is a userspace bug. All extant vector hardware traps on these misaligned accesses. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240524185600.5919-1-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2024-05-30 09:42:53 -07:00
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acpi.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
boot-image-header.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
boot.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
cmodx.rst	documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl	2024-04-18 08:10:59 -07:00
features.rst	docs: kernel_feat.py: fix potential command injection	2024-01-11 09:21:01 -07:00
hwprobe.rst	riscv: hwprobe: export Zihintpause ISA extension	2024-04-28 14:50:38 -07:00
index.rst	documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl	2024-04-18 08:10:59 -07:00
patch-acceptance.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
uabi.rst	Documentation: RISC-V: uabi: Only scalar misaligned loads are supported	2024-05-30 09:42:53 -07:00
vector.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
vm-layout.rst	docs: riscv: Define behavior of mmap	2024-03-14 08:46:15 -07:00