korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-12-26 12:34:41 +08:00
Code Issues Packages Projects Releases Wiki Activity
33b9966db3
linux/arch/arm/boot/dts/imx6q.dtsi
Linus Torvalds f83ccb9358 ARM: SoC: device tree changes 
A large part of the arm-soc patches are nowadays DT changes, adding support
 for new SoCs, boards and devices without changing kernel source. The plan
 is still to move the devicetree files out of the kernel tree and reduce
 the amount of churn going on here, but we keep finding reasons to delay
 doing that.
 
 Changes are really all over the place, with little sticking out particularly.
 We have contributions from a total of 116 people in this branch.
 
 Unfortunately, the size of this branch also causes a significant number
 of conflicts at the moment, typically when subsystem maintainers merge
 patches that change the driver at the same time as the dts files. In
 most cases this could be avoided because the dts changes are supposed
 to be compatible in both ways, and we are asking everyone to send ARM
 dts changes through our tree only.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIVAwUAUz/11WCrR//JCVInAQIIyRAA0DjdNNQ/A4G2i1nZCiTFH6a4oZy4JarN
 ATVPkW/V8avhh+yVNe5FWA44Xe6CDC5TXwMaIsbK+w3Iclj3fplh/MsBkQ9ZT9Sl
 LAjJoOjuYucCeDy0WLVioRKZ4PJEDoCu/oZTauIMnmWCOCRxLYpOM3FkAT9oN/Ti
 lswpTSLiV1/U3ZSI4M3qn+Sx1VJL8c/hAIWbvf5if2diYkWPk3VOSKyxmD9zLWdD
 Iqtb79J+ETVeOIM4sHnx79cG4ZCdpOfRAl7qx6hkJu0YATXESxWhpXVE2McTJuzM
 qHKsRRNSfsfSWPeF4angll9o06X/qgdT6C4P2dfH49lGeG7llOttw3OaCx3hWCTe
 U5bt26qtbwG2ZbzocaqvideP+rbpQrCH2vdO1embPv5Lu6peMoBWjxy6twSVXJBG
 LIymJ0IbiGYxL7BReGqRXt6ehy0BDWBeTSTdsGqgEl2TnxHuS/kgGfJc4D5riiEk
 aRPVq10p/k+yo4BZtq2GqXIOG6cqkIQ5lhl5Tg9+MfUlquAONqJP70FgRJDBIw9L
 9uJp71bgSsA6eYg2tXoqJtpdjKplDWavgtACzIkFg2qFLyYmKvx+F0AXbeTIsrri
 /mIchTyG+dgiIjWvj/Xsf7jhrdzRcl3uKsJwFmk927pIsh24HV8T+LKgHrf+sVcO
 qEsEnKGYA6s=
 =zl/N
 -----END PGP SIGNATURE-----

Merge tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device tree changes from Arnd Bergmann:
 "A large part of the arm-soc patches are nowadays DT changes, adding
  support for new SoCs, boards and devices without changing kernel
  source.  The plan is still to move the devicetree files out of the
  kernel tree and reduce the amount of churn going on here, but we keep
  finding reasons to delay doing that.

  Changes are really all over the place, with little sticking out
  particularly.  We have contributions from a total of 116 people in
  this branch.

  Unfortunately, the size of this branch also causes a significant
  number of conflicts at the moment, typically when subsystem
  maintainers merge patches that change the driver at the same time as
  the dts files.  In most cases this could be avoided because the dts
  changes are supposed to be compatible in both ways, and we are asking
  everyone to send ARM dts changes through our tree only"

* tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (541 commits)
  dts: stmmac: Document the clocks property in the stmmac base document
  dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
  ARM: STi: stih41x: Add support for the FSM Serial Flash Controller
  ARM: STi: stih416: Add support for the FSM Serial Flash Controller
  ARM: tegra: fix Dalmore pinctrl configuration
  ARM: dts: keystone: use common "ti,keystone" compatible instead of -evm
  ARM: dts: k2hk-evm: set ubifs partition size for 512M NAND
  ARM: dts: Build all keystone dt blobs
  ARM: dts: keystone: Fix control register range for clktsip
  ARM: dts: keystone: Fix domain register range for clkfftc1
  ARM: dts: bcm28155-ap: leave camldo1 on to fix reboot
  ARM: dts: add bcm590xx pmu support and enable for bcm28155-ap
  ARM: dts: bcm21664: Add device tree files.
  ARM: DT: bcm21664: Device tree bindings
  ARM: efm32: properly namespace i2c location property
  ARM: efm32: fix unit address part in USART2 device nodes' names
  ARM: mvebu: Enable NAND controller in Armada 385-DB
  ARM: mvebu: Add support for NAND controller in Armada 38x SoC
  ARM: mvebu: Add the Core Divider clock to Armada 38x SoCs
  ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCs
  ...
2014-04-05 15:29:04 -07:00

294 lines
6.3 KiB
Plaintext
Raw Blame History

/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q-pinfunc.h"
#include "imx6qdl.dtsi"
/ {
aliases {
spi4 = &ecspi5;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1150000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
1200000 1275000
996000 1250000
852000 1250000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks 104>, <&clks 6>, <&clks 16>,
<&clks 17>, <&clks 170>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
cpu@2 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
};
cpu@3 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
};
};
soc {
ocram: sram@00900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x40000>;
clocks = <&clks 142>;
};
aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
ecspi5: ecspi@02018000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
reg = <0x02018000 0x4000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 116>, <&clks 116>;
clock-names = "ipg", "per";
status = "disabled";
};
};
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6q-iomuxc";
ipu2 {
pinctrl_ipu2_1: ipu2grp-1 {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
>;
};
};
};
};
sata: sata@02200000 {
compatible = "fsl,imx6q-ahci";
reg = <0x02200000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 154>, <&clks 187>, <&clks 105>;
clock-names = "sata", "sata_ref", "ahb";
status = "disabled";
};
ipu2: ipu@02800000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ipu";
reg = <0x02800000 0x400000>;
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
<0 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 133>, <&clks 134>, <&clks 137>;
clock-names = "bus", "di0", "di1";
resets = <&src 4>;
ipu2_di0: port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
ipu2_di0_disp0: endpoint@0 {
};
ipu2_di0_hdmi: endpoint@1 {
remote-endpoint = <&hdmi_mux_2>;
};
ipu2_di0_mipi: endpoint@2 {
};
ipu2_di0_lvds0: endpoint@3 {
remote-endpoint = <&lvds0_mux_2>;
};
ipu2_di0_lvds1: endpoint@4 {
remote-endpoint = <&lvds1_mux_2>;
};
};
ipu2_di1: port@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
ipu2_di1_hdmi: endpoint@1 {
remote-endpoint = <&hdmi_mux_3>;
};
ipu2_di1_mipi: endpoint@2 {
};
ipu2_di1_lvds0: endpoint@3 {
remote-endpoint = <&lvds0_mux_3>;
};
ipu2_di1_lvds1: endpoint@4 {
remote-endpoint = <&lvds1_mux_3>;
};
};
};
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
};
};
&hdmi {
compatible = "fsl,imx6q-hdmi";
port@2 {
reg = <2>;
hdmi_mux_2: endpoint {
remote-endpoint = <&ipu2_di0_hdmi>;
};
};
port@3 {
reg = <3>;
hdmi_mux_3: endpoint {
remote-endpoint = <&ipu2_di1_hdmi>;
};
};
};
&ldb {
clocks = <&clks 33>, <&clks 34>,
<&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
<&clks 135>, <&clks 136>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel", "di2_sel", "di3_sel",
"di0", "di1";
lvds-channel@0 {
port@2 {
reg = <2>;
lvds0_mux_2: endpoint {
remote-endpoint = <&ipu2_di0_lvds0>;
};
};
port@3 {
reg = <3>;
lvds0_mux_3: endpoint {
remote-endpoint = <&ipu2_di1_lvds0>;
};
};
};
lvds-channel@1 {
port@2 {
reg = <2>;
lvds1_mux_2: endpoint {
remote-endpoint = <&ipu2_di0_lvds1>;
};
};
port@3 {
reg = <3>;
lvds1_mux_3: endpoint {
remote-endpoint = <&ipu2_di1_lvds1>;
};
};
};
};
&mipi_dsi {
port@2 {
reg = <2>;
mipi_mux_2: endpoint {
remote-endpoint = <&ipu2_di0_mipi>;
};
};
port@3 {
reg = <3>;
mipi_mux_3: endpoint {
remote-endpoint = <&ipu2_di1_mipi>;
};
};
};
Reference in New Issue View Git Blame Copy Permalink