mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-27 04:54:41 +08:00
5a0e3ad6af
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
444 lines
11 KiB
C
444 lines
11 KiB
C
/*
|
|
* Support for the GPIO/IRQ expander chips present on several HTC phones.
|
|
* These are implemented in CPLD chips present on the board.
|
|
*
|
|
* Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
|
|
* Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
|
|
*
|
|
* This file may be distributed under the terms of the GNU GPL license.
|
|
*/
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/errno.h>
|
|
#include <linux/interrupt.h>
|
|
#include <linux/irq.h>
|
|
#include <linux/io.h>
|
|
#include <linux/spinlock.h>
|
|
#include <linux/platform_device.h>
|
|
#include <linux/slab.h>
|
|
#include <linux/module.h>
|
|
#include <linux/mfd/htc-egpio.h>
|
|
|
|
struct egpio_chip {
|
|
int reg_start;
|
|
int cached_values;
|
|
unsigned long is_out;
|
|
struct device *dev;
|
|
struct gpio_chip chip;
|
|
};
|
|
|
|
struct egpio_info {
|
|
spinlock_t lock;
|
|
|
|
/* iomem info */
|
|
void __iomem *base_addr;
|
|
int bus_shift; /* byte shift */
|
|
int reg_shift; /* bit shift */
|
|
int reg_mask;
|
|
|
|
/* irq info */
|
|
int ack_register;
|
|
int ack_write;
|
|
u16 irqs_enabled;
|
|
uint irq_start;
|
|
int nirqs;
|
|
uint chained_irq;
|
|
|
|
/* egpio info */
|
|
struct egpio_chip *chip;
|
|
int nchips;
|
|
};
|
|
|
|
static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
|
|
{
|
|
writew(value, ei->base_addr + (reg << ei->bus_shift));
|
|
}
|
|
|
|
static inline u16 egpio_readw(struct egpio_info *ei, int reg)
|
|
{
|
|
return readw(ei->base_addr + (reg << ei->bus_shift));
|
|
}
|
|
|
|
/*
|
|
* IRQs
|
|
*/
|
|
|
|
static inline void ack_irqs(struct egpio_info *ei)
|
|
{
|
|
egpio_writew(ei->ack_write, ei, ei->ack_register);
|
|
pr_debug("EGPIO ack - write %x to base+%x\n",
|
|
ei->ack_write, ei->ack_register << ei->bus_shift);
|
|
}
|
|
|
|
static void egpio_ack(unsigned int irq)
|
|
{
|
|
}
|
|
|
|
/* There does not appear to be a way to proactively mask interrupts
|
|
* on the egpio chip itself. So, we simply ignore interrupts that
|
|
* aren't desired. */
|
|
static void egpio_mask(unsigned int irq)
|
|
{
|
|
struct egpio_info *ei = get_irq_chip_data(irq);
|
|
ei->irqs_enabled &= ~(1 << (irq - ei->irq_start));
|
|
pr_debug("EGPIO mask %d %04x\n", irq, ei->irqs_enabled);
|
|
}
|
|
static void egpio_unmask(unsigned int irq)
|
|
{
|
|
struct egpio_info *ei = get_irq_chip_data(irq);
|
|
ei->irqs_enabled |= 1 << (irq - ei->irq_start);
|
|
pr_debug("EGPIO unmask %d %04x\n", irq, ei->irqs_enabled);
|
|
}
|
|
|
|
static struct irq_chip egpio_muxed_chip = {
|
|
.name = "htc-egpio",
|
|
.ack = egpio_ack,
|
|
.mask = egpio_mask,
|
|
.unmask = egpio_unmask,
|
|
};
|
|
|
|
static void egpio_handler(unsigned int irq, struct irq_desc *desc)
|
|
{
|
|
struct egpio_info *ei = get_irq_data(irq);
|
|
int irqpin;
|
|
|
|
/* Read current pins. */
|
|
unsigned long readval = egpio_readw(ei, ei->ack_register);
|
|
pr_debug("IRQ reg: %x\n", (unsigned int)readval);
|
|
/* Ack/unmask interrupts. */
|
|
ack_irqs(ei);
|
|
/* Process all set pins. */
|
|
readval &= ei->irqs_enabled;
|
|
for_each_set_bit(irqpin, &readval, ei->nirqs) {
|
|
/* Run irq handler */
|
|
pr_debug("got IRQ %d\n", irqpin);
|
|
irq = ei->irq_start + irqpin;
|
|
desc = irq_to_desc(irq);
|
|
desc->handle_irq(irq, desc);
|
|
}
|
|
}
|
|
|
|
int htc_egpio_get_wakeup_irq(struct device *dev)
|
|
{
|
|
struct egpio_info *ei = dev_get_drvdata(dev);
|
|
|
|
/* Read current pins. */
|
|
u16 readval = egpio_readw(ei, ei->ack_register);
|
|
/* Ack/unmask interrupts. */
|
|
ack_irqs(ei);
|
|
/* Return first set pin. */
|
|
readval &= ei->irqs_enabled;
|
|
return ei->irq_start + ffs(readval) - 1;
|
|
}
|
|
EXPORT_SYMBOL(htc_egpio_get_wakeup_irq);
|
|
|
|
static inline int egpio_pos(struct egpio_info *ei, int bit)
|
|
{
|
|
return bit >> ei->reg_shift;
|
|
}
|
|
|
|
static inline int egpio_bit(struct egpio_info *ei, int bit)
|
|
{
|
|
return 1 << (bit & ((1 << ei->reg_shift)-1));
|
|
}
|
|
|
|
/*
|
|
* Input pins
|
|
*/
|
|
|
|
static int egpio_get(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct egpio_chip *egpio;
|
|
struct egpio_info *ei;
|
|
unsigned bit;
|
|
int reg;
|
|
int value;
|
|
|
|
pr_debug("egpio_get_value(%d)\n", chip->base + offset);
|
|
|
|
egpio = container_of(chip, struct egpio_chip, chip);
|
|
ei = dev_get_drvdata(egpio->dev);
|
|
bit = egpio_bit(ei, offset);
|
|
reg = egpio->reg_start + egpio_pos(ei, offset);
|
|
|
|
value = egpio_readw(ei, reg);
|
|
pr_debug("readw(%p + %x) = %x\n",
|
|
ei->base_addr, reg << ei->bus_shift, value);
|
|
return value & bit;
|
|
}
|
|
|
|
static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct egpio_chip *egpio;
|
|
|
|
egpio = container_of(chip, struct egpio_chip, chip);
|
|
return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Output pins
|
|
*/
|
|
|
|
static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
|
{
|
|
unsigned long flag;
|
|
struct egpio_chip *egpio;
|
|
struct egpio_info *ei;
|
|
unsigned bit;
|
|
int pos;
|
|
int reg;
|
|
int shift;
|
|
|
|
pr_debug("egpio_set(%s, %d(%d), %d)\n",
|
|
chip->label, offset, offset+chip->base, value);
|
|
|
|
egpio = container_of(chip, struct egpio_chip, chip);
|
|
ei = dev_get_drvdata(egpio->dev);
|
|
bit = egpio_bit(ei, offset);
|
|
pos = egpio_pos(ei, offset);
|
|
reg = egpio->reg_start + pos;
|
|
shift = pos << ei->reg_shift;
|
|
|
|
pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
|
|
reg, (egpio->cached_values >> shift) & ei->reg_mask);
|
|
|
|
spin_lock_irqsave(&ei->lock, flag);
|
|
if (value)
|
|
egpio->cached_values |= (1 << offset);
|
|
else
|
|
egpio->cached_values &= ~(1 << offset);
|
|
egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
|
|
spin_unlock_irqrestore(&ei->lock, flag);
|
|
}
|
|
|
|
static int egpio_direction_output(struct gpio_chip *chip,
|
|
unsigned offset, int value)
|
|
{
|
|
struct egpio_chip *egpio;
|
|
|
|
egpio = container_of(chip, struct egpio_chip, chip);
|
|
if (test_bit(offset, &egpio->is_out)) {
|
|
egpio_set(chip, offset, value);
|
|
return 0;
|
|
} else {
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static void egpio_write_cache(struct egpio_info *ei)
|
|
{
|
|
int i;
|
|
struct egpio_chip *egpio;
|
|
int shift;
|
|
|
|
for (i = 0; i < ei->nchips; i++) {
|
|
egpio = &(ei->chip[i]);
|
|
if (!egpio->is_out)
|
|
continue;
|
|
|
|
for (shift = 0; shift < egpio->chip.ngpio;
|
|
shift += (1<<ei->reg_shift)) {
|
|
|
|
int reg = egpio->reg_start + egpio_pos(ei, shift);
|
|
|
|
if (!((egpio->is_out >> shift) & ei->reg_mask))
|
|
continue;
|
|
|
|
pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
|
|
(egpio->cached_values >> shift) & ei->reg_mask,
|
|
egpio_readw(ei, reg));
|
|
|
|
egpio_writew((egpio->cached_values >> shift)
|
|
& ei->reg_mask, ei, reg);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* Setup
|
|
*/
|
|
|
|
static int __init egpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct htc_egpio_platform_data *pdata = pdev->dev.platform_data;
|
|
struct resource *res;
|
|
struct egpio_info *ei;
|
|
struct gpio_chip *chip;
|
|
unsigned int irq, irq_end;
|
|
int i;
|
|
int ret;
|
|
|
|
/* Initialize ei data structure. */
|
|
ei = kzalloc(sizeof(*ei), GFP_KERNEL);
|
|
if (!ei)
|
|
return -ENOMEM;
|
|
|
|
spin_lock_init(&ei->lock);
|
|
|
|
/* Find chained irq */
|
|
ret = -EINVAL;
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
if (res)
|
|
ei->chained_irq = res->start;
|
|
|
|
/* Map egpio chip into virtual address space. */
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
goto fail;
|
|
ei->base_addr = ioremap_nocache(res->start, resource_size(res));
|
|
if (!ei->base_addr)
|
|
goto fail;
|
|
pr_debug("EGPIO phys=%08x virt=%p\n", (u32)res->start, ei->base_addr);
|
|
|
|
if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
|
|
goto fail;
|
|
ei->bus_shift = fls(pdata->bus_width - 1) - 3;
|
|
pr_debug("bus_shift = %d\n", ei->bus_shift);
|
|
|
|
if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
|
|
goto fail;
|
|
ei->reg_shift = fls(pdata->reg_width - 1);
|
|
pr_debug("reg_shift = %d\n", ei->reg_shift);
|
|
|
|
ei->reg_mask = (1 << pdata->reg_width) - 1;
|
|
|
|
platform_set_drvdata(pdev, ei);
|
|
|
|
ei->nchips = pdata->num_chips;
|
|
ei->chip = kzalloc(sizeof(struct egpio_chip) * ei->nchips, GFP_KERNEL);
|
|
if (!ei->chip) {
|
|
ret = -ENOMEM;
|
|
goto fail;
|
|
}
|
|
for (i = 0; i < ei->nchips; i++) {
|
|
ei->chip[i].reg_start = pdata->chip[i].reg_start;
|
|
ei->chip[i].cached_values = pdata->chip[i].initial_values;
|
|
ei->chip[i].is_out = pdata->chip[i].direction;
|
|
ei->chip[i].dev = &(pdev->dev);
|
|
chip = &(ei->chip[i].chip);
|
|
chip->label = "htc-egpio";
|
|
chip->dev = &pdev->dev;
|
|
chip->owner = THIS_MODULE;
|
|
chip->get = egpio_get;
|
|
chip->set = egpio_set;
|
|
chip->direction_input = egpio_direction_input;
|
|
chip->direction_output = egpio_direction_output;
|
|
chip->base = pdata->chip[i].gpio_base;
|
|
chip->ngpio = pdata->chip[i].num_gpios;
|
|
|
|
gpiochip_add(chip);
|
|
}
|
|
|
|
/* Set initial pin values */
|
|
egpio_write_cache(ei);
|
|
|
|
ei->irq_start = pdata->irq_base;
|
|
ei->nirqs = pdata->num_irqs;
|
|
ei->ack_register = pdata->ack_register;
|
|
|
|
if (ei->chained_irq) {
|
|
/* Setup irq handlers */
|
|
ei->ack_write = 0xFFFF;
|
|
if (pdata->invert_acks)
|
|
ei->ack_write = 0;
|
|
irq_end = ei->irq_start + ei->nirqs;
|
|
for (irq = ei->irq_start; irq < irq_end; irq++) {
|
|
set_irq_chip(irq, &egpio_muxed_chip);
|
|
set_irq_chip_data(irq, ei);
|
|
set_irq_handler(irq, handle_simple_irq);
|
|
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
|
}
|
|
set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
|
|
set_irq_data(ei->chained_irq, ei);
|
|
set_irq_chained_handler(ei->chained_irq, egpio_handler);
|
|
ack_irqs(ei);
|
|
|
|
device_init_wakeup(&pdev->dev, 1);
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
printk(KERN_ERR "EGPIO failed to setup\n");
|
|
kfree(ei);
|
|
return ret;
|
|
}
|
|
|
|
static int __exit egpio_remove(struct platform_device *pdev)
|
|
{
|
|
struct egpio_info *ei = platform_get_drvdata(pdev);
|
|
unsigned int irq, irq_end;
|
|
|
|
if (ei->chained_irq) {
|
|
irq_end = ei->irq_start + ei->nirqs;
|
|
for (irq = ei->irq_start; irq < irq_end; irq++) {
|
|
set_irq_chip(irq, NULL);
|
|
set_irq_handler(irq, NULL);
|
|
set_irq_flags(irq, 0);
|
|
}
|
|
set_irq_chained_handler(ei->chained_irq, NULL);
|
|
device_init_wakeup(&pdev->dev, 0);
|
|
}
|
|
iounmap(ei->base_addr);
|
|
kfree(ei->chip);
|
|
kfree(ei);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
struct egpio_info *ei = platform_get_drvdata(pdev);
|
|
|
|
if (ei->chained_irq && device_may_wakeup(&pdev->dev))
|
|
enable_irq_wake(ei->chained_irq);
|
|
return 0;
|
|
}
|
|
|
|
static int egpio_resume(struct platform_device *pdev)
|
|
{
|
|
struct egpio_info *ei = platform_get_drvdata(pdev);
|
|
|
|
if (ei->chained_irq && device_may_wakeup(&pdev->dev))
|
|
disable_irq_wake(ei->chained_irq);
|
|
|
|
/* Update registers from the cache, in case
|
|
the CPLD was powered off during suspend */
|
|
egpio_write_cache(ei);
|
|
return 0;
|
|
}
|
|
#else
|
|
#define egpio_suspend NULL
|
|
#define egpio_resume NULL
|
|
#endif
|
|
|
|
|
|
static struct platform_driver egpio_driver = {
|
|
.driver = {
|
|
.name = "htc-egpio",
|
|
},
|
|
.remove = __exit_p(egpio_remove),
|
|
.suspend = egpio_suspend,
|
|
.resume = egpio_resume,
|
|
};
|
|
|
|
static int __init egpio_init(void)
|
|
{
|
|
return platform_driver_probe(&egpio_driver, egpio_probe);
|
|
}
|
|
|
|
static void __exit egpio_exit(void)
|
|
{
|
|
platform_driver_unregister(&egpio_driver);
|
|
}
|
|
|
|
/* start early for dependencies */
|
|
subsys_initcall(egpio_init);
|
|
module_exit(egpio_exit)
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Kevin O'Connor <kevin@koconnor.net>");
|